Date: Mon, 19 Feb 2007 10:04:33 +1300 From: Andrew Turner <andrew@fubar.geek.nz> To: freebsd-ppc@freebsd.org Subject: Patch to partially boot an EFIKA Message-ID: <20070219100433.66d7ff49@hermies.int.fubar.geek.nz>
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--MP_2T7mzsrHA=2RIWRHB2KGn7J Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Content-Disposition: inline The attached patch helps me to partially boot my EFIKA. The file ofwread.S is from NetBSD and needs to be placed in sys/powerpc/powerpc. The patch takes the real-mode ofw interface code from NetBSD and the TLB exception handlers from //depot/user/jaras in perforce. The call to ofwr_init in locore.S is not enabled by default as it doesn't currently work on my Apple. By commenting out the FIRMWORKSBUGS ifdef, to call ofwr_init, I can get my EFIKA to boot until it attempts to schedule work. Andrew --MP_2T7mzsrHA=2RIWRHB2KGn7J Content-Type: application/octet-stream; name=ofwreal.S Content-Transfer-Encoding: base64 Content-Disposition: attachment; filename=ofwreal.S LyoJJE5ldEJTRDogb2Z3cmVhbC5TLHYgMS45IDIwMDcvMDEvMTQgMjI6MTE6MjcgYXltZXJpYyBF eHAgJAkqLwoKLyoKICogQ29weXJpZ2h0IChDKSAxOTk2IFdvbGZnYW5nIFNvbGZyYW5rLgogKiBD b3B5cmlnaHQgKEMpIDE5OTYgVG9vTHMgR21iSC4KICogQWxsIHJpZ2h0cyByZXNlcnZlZC4KICoK ICogUmVkaXN0cmlidXRpb24gYW5kIHVzZSBpbiBzb3VyY2UgYW5kIGJpbmFyeSBmb3Jtcywgd2l0 aCBvciB3aXRob3V0CiAqIG1vZGlmaWNhdGlvbiwgYXJlIHBlcm1pdHRlZCBwcm92aWRlZCB0aGF0 IHRoZSBmb2xsb3dpbmcgY29uZGl0aW9ucwogKiBhcmUgbWV0OgogKiAxLiBSZWRpc3RyaWJ1dGlv bnMgb2Ygc291cmNlIGNvZGUgbXVzdCByZXRhaW4gdGhlIGFib3ZlIGNvcHlyaWdodAogKiAgICBu b3RpY2UsIHRoaXMgbGlzdCBvZiBjb25kaXRpb25zIGFuZCB0aGUgZm9sbG93aW5nIGRpc2NsYWlt ZXIuCiAqIDIuIFJlZGlzdHJpYnV0aW9ucyBpbiBiaW5hcnkgZm9ybSBtdXN0IHJlcHJvZHVjZSB0 aGUgYWJvdmUgY29weXJpZ2h0CiAqICAgIG5vdGljZSwgdGhpcyBsaXN0IG9mIGNvbmRpdGlvbnMg YW5kIHRoZSBmb2xsb3dpbmcgZGlzY2xhaW1lciBpbiB0aGUKICogICAgZG9jdW1lbnRhdGlvbiBh bmQvb3Igb3RoZXIgbWF0ZXJpYWxzIHByb3ZpZGVkIHdpdGggdGhlIGRpc3RyaWJ1dGlvbi4KICog My4gQWxsIGFkdmVydGlzaW5nIG1hdGVyaWFscyBtZW50aW9uaW5nIGZlYXR1cmVzIG9yIHVzZSBv ZiB0aGlzIHNvZnR3YXJlCiAqICAgIG11c3QgZGlzcGxheSB0aGUgZm9sbG93aW5nIGFja25vd2xl ZGdlbWVudDoKICoJVGhpcyBwcm9kdWN0IGluY2x1ZGVzIHNvZnR3YXJlIGRldmVsb3BlZCBieSBU b29McyBHbWJILgogKiA0LiBUaGUgbmFtZSBvZiBUb29McyBHbWJIIG1heSBub3QgYmUgdXNlZCB0 byBlbmRvcnNlIG9yIHByb21vdGUgcHJvZHVjdHMKICogICAgZGVyaXZlZCBmcm9tIHRoaXMgc29m dHdhcmUgd2l0aG91dCBzcGVjaWZpYyBwcmlvciB3cml0dGVuIHBlcm1pc3Npb24uCiAqCiAqIFRI SVMgU09GVFdBUkUgSVMgUFJPVklERUQgQlkgVE9PTFMgR01CSCBgYEFTIElTJycgQU5EIEFOWSBF WFBSRVNTIE9SCiAqIElNUExJRUQgV0FSUkFOVElFUywgSU5DTFVESU5HLCBCVVQgTk9UIExJTUlU RUQgVE8sIFRIRSBJTVBMSUVEIFdBUlJBTlRJRVMKICogT0YgTUVSQ0hBTlRBQklMSVRZIEFORCBG SVRORVNTIEZPUiBBIFBBUlRJQ1VMQVIgUFVSUE9TRSBBUkUgRElTQ0xBSU1FRC4KICogSU4gTk8g RVZFTlQgU0hBTEwgVE9PTFMgR01CSCBCRSBMSUFCTEUgRk9SIEFOWSBESVJFQ1QsIElORElSRUNU LCBJTkNJREVOVEFMLAogKiBTUEVDSUFMLCBFWEVNUExBUlksIE9SIENPTlNFUVVFTlRJQUwgREFN QUdFUyAoSU5DTFVESU5HLCBCVVQgTk9UIExJTUlURUQgVE8sCiAqIFBST0NVUkVNRU5UIE9GIFNV QlNUSVRVVEUgR09PRFMgT1IgU0VSVklDRVM7IExPU1MgT0YgVVNFLCBEQVRBLCBPUiBQUk9GSVRT OwogKiBPUiBCVVNJTkVTUyBJTlRFUlJVUFRJT04pIEhPV0VWRVIgQ0FVU0VEIEFORCBPTiBBTlkg VEhFT1JZIE9GIExJQUJJTElUWSwKICogV0hFVEhFUiBJTiBDT05UUkFDVCwgU1RSSUNUIExJQUJJ TElUWSwgT1IgVE9SVCAoSU5DTFVESU5HIE5FR0xJR0VOQ0UgT1IKICogT1RIRVJXSVNFKSBBUklT SU5HIElOIEFOWSBXQVkgT1VUIE9GIFRIRSBVU0UgT0YgVEhJUyBTT0ZUV0FSRSwgRVZFTiBJRgog KiBBRFZJU0VEIE9GIFRIRSBQT1NTSUJJTElUWSBPRiBTVUNIIERBTUFHRS4KICovCgovKgogKiBU aGlzIGZpbGUgcHJvdmlkZXMgYSByZWFsLW1vZGUgY2xpZW50IGludGVyZmFjZSBvbiBtYWNoaW5l cywgdGhhdAogKiAoaW5jb3JyZWN0bHkpIG9ubHkgaW1wbGVtZW50IHZpcnR1YWwgbW9kZSBjbGll bnQgaW50ZXJmYWNlLgogKgogKiBJdCBhc3N1bWVzIHRob3VnaCwgdGhhdCBhbnkgYWN0dWFsIG1l bW9yeSBpbiB0aGUgbWFjaGluZSBpcwogKiBtYXBwZWQgMToxIGV2ZW4gYnkgdGhlIHZpcnR1YWwg bW9kZSBPcGVuRmlybXdhcmUuCiAqIEZ1cnRoZXJtb3JlIGl0IGFzc3VtZXMgdGhhdCBhZGRyZXNz ZXMgcmV0dXJuZWQgYnkgT3BlbkZpcm13YXJlIGFyZSBub3QKICogYWNjZXNzZWQgYnkgdGhlIGNs aWVudC4KICoKICogVE9ETzogaGFuZGxlIHNldC1jYWxsYmFjayBzcGVjaWFsbHkKICovCiNpbmNs dWRlIDxtYWNoaW5lL3BzbC5oPgojaW5jbHVkZSA8bWFjaGluZS90cmFwLmg+CiNkZWZpbmUgX05P UkVHTkFNRVMKI2luY2x1ZGUgPG1hY2hpbmUvYXNtLmg+CgojZGVmaW5lCUNBQ0hFTElORQkzMgkJ LyogTm90ZSB0aGF0IHRoaXMgdmFsdWUgaXMgcmVhbGx5CgkJCQkJICAgaGFyZHdpcmVkICovCgoJ LmRhdGEKb2ZlbnRyeToKCS5sb25nCTAJCQkvKiBhY3R1YWwgZW50cnkgdG8gZmlybXdhcmUgaW4K CQkJCQkgICB2aXJ0dWFsIG1vZGUgKi8KCiNkZWZpbmUJQkFUU0laRQkJKDgqOCkKI2RlZmluZQlT UlNJWkUJCSgxNio0KQojZGVmaW5lCVNQUkdTSVpFCSg0KjQpCiNkZWZpbmUJU0RSMVNJWkUJNAoj ZGVmaW5lCVNJMVNJWkUJCSgyKjI1NikKI2RlZmluZQlTSTJTSVpFCQkoMyoyNTYpCiNkZWZpbmUJ U1ZTSVpFCQkoQkFUU0laRStTUlNJWkUrU1BSR1NJWkUrU0RSMVNJWkUrU0kxU0laRStTSTJTSVpF KQoKCS5sb2NhbAlmd3NhdmUKCS5jb21tCWZ3c2F2ZSxTVlNJWkUsOAoKCS5sb2NhbAljbHNhdmUK CS5jb21tCWNsc2F2ZSxTVlNJWkUsOAoKRU5UUlkob2Z3cl9pbml0KQoJbWZscgklcjMxCQkJLyog c2F2ZSByZXR1cm4gYWRkcmVzcyAqLwoKCW1yCSVyMTMsJXI2CQkvKiBzYXZlIGFyZ3MgKi8KCW1y CSVyMTIsJXI3CQkvKiBzYXZlIGFyZ3NsZW4gKi8KCWxpcwklcjgsb2ZlbnRyeUBoYQoJc3R3CSVy NSxvZmVudHJ5QGwoJXI4KQkvKiBzYXZlIHZpcnR1YWwgbW9kZSBmaXJtd2FyZSBlbnRyeSAqLwoK CWxpcwklcjMsZndzYXZlQGhhCQkvKiBzYXZlIHRoZSBtbXUgdmFsdWVzIG9mIHRoZQoJCQkJCSAg IGZpcm13YXJlICovCglhZGRpCSVyMywlcjMsZndzYXZlQGwKCWJsCXNhdmVtbXUKCglsaXMJJXI1 LGZ3ZW50cnlAaGEJCS8qIGdldCBuZXcgZmlybXdhcmUgZW50cnkgKi8KCWFkZGkJJXI1LCVyNSxm d2VudHJ5QGwKCgltcgklcjYsJXIxMwkJLyogcmVzdG9yZSBhcmdzIHBvaW50ZXIgKi8KCW1yCSVy NywlcjEyCQkvKiByZXN0b3JlIGFyZ3MgbGVuZ3RoICovCgltdGxyCSVyMzEJCQkvKiByZXN0b3Jl IHJldHVybiBhZGRyZXNzICovCglibHIKCi8qCiAqIEVtdWxhdGVkIGZpcm13YXJlIGVudHJ5Lgog Ki8KZndlbnRyeToKCW1mbHIJJXIwCQkJLyogc2F2ZSByZXR1cm4gYWRkcmVzcyAqLwoJc3R3CSVy MCw0KCVyMSkKCXN0d3UJJXIxLC0xNiglcjEpCQkvKiBzZXR1cCBzdGFjayBmcmFtZSAqLwoJc3R3 CSVyMyw4KCVyMSkJCS8qIHNhdmUgYXJnICovCgoJbGlzCSVyMyxjbHNhdmVAaGEJCS8qIHNhdmUg bW11IHZhbHVlcyBvZiBjbGllbnQgKi8KCWFkZGkJJXIzLCVyMyxjbHNhdmVAbAoJYmwJc2F2ZW1t dQoKCWxpcwklcjMsZndzYXZlQGhhCQkvKiByZXN0b3JlIG1tdSB2YWx1ZXMgb2YgZmlybXdhcmUg Ki8KCWFkZGkJJXIzLCVyMyxmd3NhdmVAbAoJYmwJcmVzdG9yZW1tdQoKCWxpcwklcjMsb2ZlbnRy eUBoYQoJbHd6CSVyMyxvZmVudHJ5QGwoJXIzKQkvKiBnZXQgYWN0dWFsIGZpcm13YXJlIGVudHJ5 ICovCgltdGxyCSVyMwoKCW1mbXNyCSVyNAoJc3R3CSVyNCwxMiglcjEpCQkvKiBzYXZlIE1TUiAq LwoJb3JpCSVyNCwlcjQsUFNMX0lSfFBTTF9EUgkvKiB0dXJuIG9uIE1NVSAqLwoJYW5kaS4JJXI0 LCVyNCx+UFNMX0VFQGwJLyogdHVybiBvZmYgaW50ZXJydXB0cyAqLwoJbXRtc3IJJXI0Cglpc3lu YwoKCWx3egklcjMsOCglcjEpCQkvKiByZXN0b3JlIGFyZyAqLwoJYmxybAkJCQkvKiBkbyBhY3R1 YWwgZmlybXdhcmUgY2FsbCAqLwoJc3R3CSVyMyw4KCVyMSkJCS8qIHNhdmUgcmV0dXJuIHZhbHVl ICovCgoJbHd6CSVyNCwxMiglcjEpCQkvKiBnZXQgc2F2ZWQgTVNSICovCgltdG1zcgklcjQKCWlz eW5jCgoJbGlzCSVyMyxmd3NhdmVAaGEJCS8qIHNhdmUgbW11IHZhbHVlcyBvZiBmaXJtYXJlICov CglhZGRpCSVyMywlcjMsZndzYXZlQGwJLyogKG1pZ2h0IG5vdCBiZSBuZWNlc3NhcnksIGJ1dC4u LiAqLwoJYmwJc2F2ZW1tdQoKCWxpcwklcjMsY2xzYXZlQGhhCQkvKiByZXN0b3JlIG1tdSB2YWx1 ZXMgb2YgY2xpZW50ICovCglhZGRpCSVyMywlcjMsY2xzYXZlQGwKCWJsCXJlc3RvcmVtbXUKCgls d3oJJXIzLDgoJXIxKQkJLyogcmVzdG9yZSByZXR1cm4gdmFsdWUgKi8KCWx3egklcjEsMCglcjEp CQkvKiBhbmQgcmV0dXJuICovCglsd3oJJXIwLDQoJXIxKQoJbXRscgklcjAKCWJscgoKLyoKICog U2F2ZSBldmVyeXRpbmcgcmVsYXRlZCB0byB0aGUgbW11IHRvIHRoZSBzYXZlYXJlIHBvaW50ZWQg dG8gYnkgcjMuCiAqLwpzYXZlbW11OgoKCW1maWJhdGwJJXI0LDAJCQkvKiBzYXZlIEJBVHMgKi8K CXN0dwklcjQsMCglcjMpCgltZmliYXR1CSVyNCwwCglzdHcJJXI0LDQoJXIzKQoJbWZpYmF0bAkl cjQsMQoJc3R3CSVyNCw4KCVyMykKCW1maWJhdHUJJXI0LDEKCXN0dwklcjQsMTIoJXIzKQoJbWZp YmF0bAklcjQsMgoJc3R3CSVyNCwxNiglcjMpCgltZmliYXR1CSVyNCwyCglzdHcJJXI0LDIwKCVy MykKCW1maWJhdGwJJXI0LDMKCXN0dwklcjQsMjQoJXIzKQoJbWZpYmF0dQklcjQsMwoJc3R3CSVy NCwyOCglcjMpCgltZmRiYXRsCSVyNCwwCglzdHcJJXI0LDMyKCVyMykKCW1mZGJhdHUJJXI0LDAK CXN0dwklcjQsMzYoJXIzKQoJbWZkYmF0bAklcjQsMQoJc3R3CSVyNCw0MCglcjMpCgltZmRiYXR1 CSVyNCwxCglzdHcJJXI0LDQ0KCVyMykKCW1mZGJhdGwJJXI0LDIKCXN0dwklcjQsNDgoJXIzKQoJ bWZkYmF0dQklcjQsMgoJc3R3CSVyNCw1MiglcjMpCgltZmRiYXRsCSVyNCwzCglzdHcJJXI0LDU2 KCVyMykKCW1mZGJhdHUJJXI0LDMKCXN0d3UJJXI0LDYwKCVyMykKCglsaQklcjQsMAkJCS8qIHNh dmUgU1JzICovCjE6CglhZGRpcwklcjQsJXI0LC0weDEwMDAwMDAwQGhhCglvci4JJXI0LCVyNCwl cjQKCW1mc3JpbgklcjUsJXI0CglzdHd1CSVyNSw0KCVyMykKCWJuZQkxYgoKCW1mc3ByZzAJJXI0 CQkJLyogc2F2ZSBTUFJHcyAqLwoJc3R3CSVyNCw0KCVyMykKCW1mc3ByZzEJJXI0CglzdHcJJXI0 LDgoJXIzKQoJbWZzcHJnMgklcjQKCXN0dwklcjQsMTIoJXIzKQoJbWZzcHJnMwklcjQKCXN0dwkl cjQsMTYoJXIzKQoKCW1mc2RyMQklcjQJCQkvKiBzYXZlIFNEUjEgKi8KCXN0dwklcjQsMjAoJXIz KQoKCWFkZGkJJXI0LCVyMywyNAoJbWZscgklcjExCglsaQklcjMsRVhDX0RTSQkJLyogc2F2ZSBE U0kvSVNJIHRyYXAgdmVjdG9ycyAqLwoJbGkJJXI1LFNJMVNJWkUKCWJsCWNvcHkKCgltdGxyCSVy MTEKCWxpCSVyMyxFWENfSU1JU1MJCS8qIHNhdmUgTUlTUyB0cmFwIHZlY3RvcnMgKi8KCWxpCSVy NSxTSTJTSVpFCgovKiBDb3B5IGFuIGV4Y2VwdGlvbiBoYW5kbGVyICovCmNvcHk6CglsaQklcjYs Q0FDSEVMSU5FCjE6Cglsd3oJJXI3LDAoJXIzKQoJbHd6CSVyOCw0KCVyMykKCWx3egklcjksOCgl cjMpCglsd3oJJXIxMCwxMiglcjMpCglzdHcJJXI3LDAoJXI0KQoJc3R3CSVyOCw0KCVyNCkKCXN0 dwklcjksOCglcjQpCglzdHcJJXIxMCwxMiglcjQpCglsd3oJJXI3LDE2KCVyMykKCWx3egklcjgs MjAoJXIzKQoJbHd6CSVyOSwyNCglcjMpCglsd3oJJXIxMCwyOCglcjMpCglzdHcJJXI3LDE2KCVy NCkKCXN0dwklcjgsMjAoJXI0KQoJc3R3CSVyOSwyNCglcjQpCglzdHcJJXIxMCwyOCglcjQpCglk Y2JzdAklcjAsJXI0CglpY2JpCSVyMCwlcjQKCWFkZAklcjMsJXIzLCVyNgoJYWRkCSVyNCwlcjQs JXI2CglzdWJmLgklcjUsJXI2LCVyNQoJYmd0CTFiCgoJZGNic3QJJXIwLCVyNAoJaWNiaQklcjAs JXI0CgoJc3luYwoJaXN5bmMKCglibHIKCi8qCiAqIFJlc3RvcmUgZXZlcnl0aW5nIHJlbGF0ZWQg dG8gdGhlIG1tdSBmcm9tIHRoZSBzYXZlYXJlIHBvaW50ZWQgdG8gYnkgcjMuCiAqLwpyZXN0b3Jl bW11OgoJbWZtc3IJJXIxMgoJYW5kaS4JJXI0LCVyMTIsfihQU0xfSVJ8UFNMX0RSKUBsCgltdG1z cgklcjQJCQkvKiBEaXNhYmxlIE1NVSAqLwoJaXN5bmMKCglsaQklcjQsMAkJCS8qIGZpcnN0LCBp bnZhbGlkYXRlIEJBVHMgKi8KCW10aWJhdHUJMCwlcjQKCW10aWJhdHUJMSwlcjQKCW10aWJhdHUJ MiwlcjQKCW10aWJhdHUJMywlcjQKCW10ZGJhdHUJMCwlcjQKCW10ZGJhdHUJMSwlcjQKCW10ZGJh dHUJMiwlcjQKCW10ZGJhdHUJMywlcjQKCglsd3oJJXI0LDAoJXIzKQoJbXRpYmF0bAkwLCVyNAkJ CS8qIHJlc3RvcmUgQkFUcyAqLwoJbHd6CSVyNCw0KCVyMykKCW10aWJhdHUJMCwlcjQKCWx3egkl cjQsOCglcjMpCgltdGliYXRsCTEsJXI0Cglsd3oJJXI0LDEyKCVyMykKCW10aWJhdHUJMSwlcjQK CWx3egklcjQsMTYoJXIzKQoJbXRpYmF0bAkyLCVyNAoJbHd6CSVyNCwyMCglcjMpCgltdGliYXR1 CTIsJXI0Cglsd3oJJXI0LDI0KCVyMykKCW10aWJhdGwJMywlcjQKCWx3egklcjQsMjgoJXIzKQoJ bXRpYmF0dQkzLCVyNAoJbHd6CSVyNCwzMiglcjMpCgltdGRiYXRsCTAsJXI0Cglsd3oJJXI0LDM2 KCVyMykKCW10ZGJhdHUJMCwlcjQKCWx3egklcjQsNDAoJXIzKQoJbXRkYmF0bAkxLCVyNAoJbHd6 CSVyNCw0NCglcjMpCgltdGRiYXR1CTEsJXI0Cglsd3oJJXI0LDQ4KCVyMykKCW10ZGJhdGwJMiwl cjQKCWx3egklcjQsNTIoJXIzKQoJbXRkYmF0dQkyLCVyNAoJbHd6CSVyNCw1NiglcjMpCgltdGRi YXRsCTMsJXI0Cglsd3p1CSVyNCw2MCglcjMpCgltdGRiYXR1CTMsJXI0CgoJbGkJJXI0LDAJCQkv KiByZXN0b3JlIFNScyAqLwoxOgoJbHd6dQklcjUsNCglcjMpCglhZGRpcwklcjQsJXI0LC0weDEw MDAwMDAwQGhhCglvci4JJXI0LCVyNCwlcjQKCW10c3JpbgklcjUsJXI0CglibmUJMWIKCglsd3oJ JXI0LDQoJXIzKQoJbXRzcHJnMAklcjQJCQkvKiByZXN0b3JlIFNQUkdzICovCglsd3oJJXI0LDgo JXIzKQoJbXRzcHJnMQklcjQKCWx3egklcjQsMTIoJXIzKQoJbXRzcHJnMgklcjQKCWx3egklcjQs MTYoJXIzKQoJbXRzcHJnMwklcjQKCglzeW5jCQkJCS8qIHJlbW92ZSBldmVyeXRoaW5nIGZyb20g dGxiICovCglsaXMJJXI0LDB4NDAwMDBAaGEKCWxpCSVyNSwweDEwMDAKMToKCXN1YmYuCSVyNCwl cjUsJXI0Cgl0bGJpZQklcjQKCWJuZQkxYgoKCXN5bmMKCXRsYnN5bmMKCXN5bmMKCglsd3oJJXI0 LDIwKCVyMykKCXN5bmMKCW10c2RyMQklcjQJCQkvKiByZXN0b3JlIFNEUjEgKi8KCglhZGRpCSVy MywlcjMsMjQKCW1mbHIJJXIxMQoJbGkJJXI0LEVYQ19EU0kJCS8qIHJlc3RvcmUgRFNJL0lTSSB0 cmFwIHZlY3RvcnMgKi8KCWxpCSVyNSxTSTFTSVpFCglibAljb3B5CgoJbGkJJXI0LEVYQ19JTUlT UwkJLyogcmVzdG9yZSBNSVNTIHRyYXAgdmVjdG9ycyAqLwoJbGkJJXI1LFNJMlNJWkUKCWJsCWNv cHkKCgkvKiB0bGJpYSAqLwoJc3luYwoJbGkJJXIzLDB4NDAKCW10Y3RyCSVyMwoJbGkJJXI0LDAK ICAgIDE6Cgl0bGJpZQklcjQKCWFkZGkJJXI0LCVyNCwweDEwMDAKCWJkbnoJMWIKCXN5bmMKCXRs YnN5bmMKCXN5bmMKCgltdG1zcgklcjEyCQkJLyogcmVzdG9yZSBNTVUgKi8KCW10bHIJJXIxMQoJ YmxyCg== --MP_2T7mzsrHA=2RIWRHB2KGn7J Content-Type: text/x-patch; name=freebsd-ppc-efika.diff Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename=freebsd-ppc-efika.diff Index: sys/conf/files.powerpc =================================================================== RCS file: /cvsroot/src/sys/conf/files.powerpc,v retrieving revision 1.60 diff -u -r1.60 files.powerpc --- sys/conf/files.powerpc 23 Oct 2006 13:05:01 -0000 1.60 +++ sys/conf/files.powerpc 8 Jan 2007 09:21:55 -0000 @@ -56,6 +56,7 @@ powerpc/powerpc/nexus.c standard powerpc/powerpc/ofwmagic.S standard powerpc/powerpc/ofw_machdep.c standard +powerpc/powerpc/ofwreal.S standard powerpc/powerpc/openpic.c standard powerpc/powerpc/pic_if.m standard powerpc/powerpc/pmap_dispatch.c standard Index: sys/powerpc/include/psl.h =================================================================== RCS file: /cvsroot/src/sys/powerpc/include/psl.h,v retrieving revision 1.4 diff -u -r1.4 psl.h --- sys/powerpc/include/psl.h 7 Jan 2005 02:29:19 -0000 1.4 +++ sys/powerpc/include/psl.h 18 Feb 2007 20:47:41 -0000 @@ -46,6 +46,7 @@ */ #define PSL_VEC 0x02000000 /* AltiVec vector unit available */ #define PSL_POW 0x00040000 /* power management */ +#define PSL_TGPR 0x00020000 /* temp. gpr remapping (mpc603e) */ #define PSL_ILE 0x00010000 /* interrupt endian mode (1 == le) */ #define PSL_EE 0x00008000 /* external interrupt enable */ #define PSL_PR 0x00004000 /* privilege mode (1 == user) */ Index: sys/powerpc/powerpc/locore.S =================================================================== RCS file: /cvsroot/src/sys/powerpc/powerpc/locore.S,v retrieving revision 1.22 diff -u -r1.22 locore.S --- sys/powerpc/powerpc/locore.S 30 Oct 2005 21:29:59 -0000 1.22 +++ sys/powerpc/powerpc/locore.S 18 Feb 2007 20:40:25 -0000 @@ -66,6 +66,7 @@ #include <machine/spr.h> #include <machine/psl.h> #include <machine/asm.h> +#include <machine/pte.h> /* Locate the per-CPU data structure */ #define GET_CPUINFO(r) \ Index: sys/powerpc/powerpc/machdep.c =================================================================== RCS file: /cvsroot/src/sys/powerpc/powerpc/machdep.c,v retrieving revision 1.100 diff -u -r1.100 machdep.c --- sys/powerpc/powerpc/machdep.c 12 Feb 2007 08:59:33 -0000 1.100 +++ sys/powerpc/powerpc/machdep.c 18 Feb 2007 20:40:45 -0000 @@ -253,6 +253,9 @@ extern void *extint, *extsize; extern void *dblow, *dbsize; extern void *vectrap, *vectrapsize; +extern void *imisstrap, *imisssize; +extern void *dlmisstrap, *dlmisssize; +extern void *dsmisstrap, *dsmisssize; void powerpc_init(u_int startkernel, u_int endkernel, u_int basekernel, void *mdp) @@ -347,6 +350,9 @@ bcopy(&trapcode, (void *)EXC_VECAST, (size_t)&trapsize); bcopy(&trapcode, (void *)EXC_THRM, (size_t)&trapsize); bcopy(&trapcode, (void *)EXC_BPT, (size_t)&trapsize); + bcopy(&imisstrap, (void *)EXC_IMISS, (size_t)&imisssize); + bcopy(&dlmisstrap, (void *)EXC_DLMISS, (size_t)&dlmisssize); + bcopy(&dsmisstrap, (void *)EXC_DSMISS, (size_t)&dsmisssize); #ifdef KDB bcopy(&dblow, (void *)EXC_RST, (size_t)&dbsize); bcopy(&dblow, (void *)EXC_MCHK, (size_t)&dbsize); Index: sys/powerpc/powerpc/trap_subr.S =================================================================== RCS file: /cvsroot/src/sys/powerpc/powerpc/trap_subr.S,v retrieving revision 1.16 diff -u -r1.16 trap_subr.S --- sys/powerpc/powerpc/trap_subr.S 23 Dec 2005 13:05:27 -0000 1.16 +++ sys/powerpc/powerpc/trap_subr.S 18 Feb 2007 20:54:16 -0000 @@ -284,6 +284,292 @@ CNAME(alisize) = .-CNAME(alitrap) /* + * It's G2 specific. Instuction TLB miss. + */ + .globl CNAME(imisstrap),CNAME(imisssize) +CNAME(imisstrap): +/* + * Instruction TLB miss flow + * Entry: + * Vec = 1000 + * srr0 -> address of instruction that missed + * srr1 -> 0:3=cr0 4=lru way bit 16:31 = saved MSR + * msr<tgpr> -> 1 + * iMiss -> ea that missed + * iCmp -> the compare value for the va that missed + * hash1 -> pointer to first hash pteg + * hash2 -> pointer to second hash pteg + * + * Register usage: + * r0 is saved counter + * r1 is junk + * r2 is pointer to pteg + * r3 is current compare value + */ + + mfspr %r2, SPR_HASH1 /* get first pointer */ + addi %r1, 0, 8 /* load 8 for counter */ + mfctr %r0 /* save counter */ + mfspr %r3, SPR_ICMP /* get first compare value */ + addi %r2, %r2, -8 /* pre dec the pointer */ +im0: + mtctr %r1 /* load counter */ +im1: + lwzu %r1, 8(%r2) /* get next pte */ + cmp 0, %r1, %r3 /* see if found pte */ + bdnzf 2, im1 /* dec count br if cmp ne and if count not zero */ + bne instrSecHash /* if not found set up second hash or exit */ + lwz %r1, +4(%r2) /* load tlb entry lower-word */ + andi. %r3, %r1, 8 /* check G bit */ + bne doISIp /* if guarded, take an ISI */ + mtctr %r0 /* restore counter */ + mfspr %r0, SPR_IMISS /* get the miss address for the tlbli */ + mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */ + mtcrf 0x80, %r3 /* restore CR0 */ + mtspr SPR_RPA, %r1 /* set the pte */ + ori %r1, %r1, 0x100 /* set reference bit */ + srwi %r1, %r1, 8 /* get byte 7 of pte */ + tlbli %r0 /* load the itlb */ + stb %r1, +6(%r2) /* update page table */ + rfi /* return to executing program */ +/* + * register usage: + * r0 is saved counter + * r1 is junk + * r2 is pointer to pteg + * r3 is current compare value + */ +instrSecHash: + andi. %r1, %r3, 0x0040 /* see if we have done second hash */ + bne doISI /* if so, go to ISI interrupt */ + mfspr %r2, SPR_HASH2 /* get the second pointer */ + ori %r3, %r3, 0x0040 /* change the compare value */ + addi %r1, %r0, 8 /* load 8 for counter */ + addi %r2, %r2, -8 /* pre dec for update on load */ + b im0 /* try second hash */ +/* + * entry Not Found: synthesize an ISI interrupt + * guarded memory protection violation: synthesize an ISI interrupt + * Entry: + * r0 is saved counter + * r1 is junk + * r2 is pointer to pteg + * r3 is current compare value + */ + +doISIp: + mfspr %r3, SPR_SRR1 /* get srr1 */ + andi. %r2, %r3, 0xffff /* clean upper srr1 */ + addis %r2, %r2, 0x0800 /* or in srr<4> = 1 to flag prot violation */ + b isi1 +doISI: + mfspr %r3, SPR_SRR1 /* get srr1 */ + andi. %r2, %r3, 0xffff /* clean srr1 */ + addis %r2, %r2, 0x4000 /* or in srr1<1> = 1 to flag pte not found */ +isi1: + mtctr %r0 /* restore counter */ + mtspr SPR_SRR1, %r2 /* set srr1 */ + mfmsr %r0 /* get msr */ + xoris %r0, %r0, 0x2 /* flip the msr<tgpr> bit */ + mtcrf 0x80, %r3 /* restore CR0 */ + mtmsr %r0 /* flip back to the native gprs */ + ba 0x400 /* go to instr. access interrupt */ + +CNAME(imisssize) = .-CNAME(imisstrap) + +/* + * It's G2 specific. Data load TLB miss. + */ + .globl CNAME(dlmisstrap),CNAME(dlmisssize) +CNAME(dlmisstrap): +/* + * Data TLB miss flow + * Entry: + * Vec = 1100 + * srr0 -> address of instruction that caused data tlb miss + * srr1 -> 0:3=cr0 4=lru way bit 5=1 if store 16:31 = saved MSR + * msr<tgpr> -> 1 + * dMiss -> ea that missed + * dCmp -> the compare value for the va that missed + * hash1 -> pointer to first hash pteg + * hash2 -> pointer to second hash pteg + * + * Register usage: + * r0 is saved counter + * r1 is junk + * r2 is pointer to pteg + * r3 is current compare value + */ + + mfspr %r2, SPR_HASH1 /* get first pointer */ + addi %r1, 0, 8 /* load 8 for counter */ + mfctr %r0 /* save counter */ + mfspr %r3, SPR_DCMP /* get first compare value */ + addi %r2, %r2, -8 /* pre dec the pointer */ +dm0: + mtctr %r1 /* load counter */ +dm1: + lwzu %r1, 8(%r2) /* get next pte */ + cmp 0, 0, %r1, %r3 /* see if found pte */ + bdnzf 2, dm1 /* dec count br if cmp ne and if count not zero */ + bne dataSecHash /* if not found set up second hash or exit */ + lwz %r1, +4(%r2) /* load tlb entry lower-word */ + mtctr %r0 /* restore counter */ + mfspr %r0, SPR_DMISS /* get the miss address for the tlbld */ + mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */ + mtcrf 0x80, %r3 /* restore CR0 */ + mtspr SPR_RPA, %r1 /* set the pte */ + ori %r1, %r1, 0x100 /* set reference bit */ + srwi %r1, %r1, 8 /* get byte 7 of pte */ + tlbld %r0 /* load the dtlb */ + stb %r1, +6(%r2) /* update page table */ + rfi /* return to executing program */ +/* + * Register usage: + * r0 is saved counter + * r1 is junk + * r2 is pointer to pteg + * r3 is current compare value + */ + +dataSecHash: + andi. %r1, %r3, 0x0040 /* see if we have done second hash */ + bne doDSI /* if so, go to DSI interrupt */ + mfspr %r2, SPR_HASH2 /* get the second pointer */ + ori %r3, %r3, 0x0040 /* change the compare value */ + addi %r1, 0, 8 /* load 8 for counter */ + addi %r2, %r2, -8 /* pre dec for update on load */ + b dm0 /* try second hash */ + +CNAME(dlmisssize) = .-CNAME(dlmisstrap) + +/* + * It's G2 specific. Data store TLB miss. + */ + .globl CNAME(dsmisstrap),CNAME(dsmisssize) +CNAME(dsmisstrap): + +/* + * Data TLB miss flow + * C=0 in dtlb and dtlb miss on store flow + * Entry: + * Vec = 1200 + * srr0 -> address of store that caused the interrupt + * srr1 -> 0:3=cr0 4=lru way bit 5=1 16:31 = saved MSR + * msr<tgpr> -> 1 + * dMiss -> ea that missed + * dCmp -> the compare value for the va that missed + * hash1 -> pointer to first hash pteg + * hash2 -> pointer to second hash pteg + * + * Register usage: + * r0 is saved counter + * r1 is junk + * r2 is pointer to pteg + * r3 is current compare value + */ + mfspr %r2, SPR_HASH1 /* get first pointer */ + addi %r1, 0, 8 /* load 8 for counter */ + mfctr %r0 /* save counter */ + mfspr %r3, SPR_DCMP /* get first compare value */ + addi %r2, %r2, -8 /* pre dec the pointer */ +ceq0: + mtctr %r1 /* load counter */ +ceq1: + lwzu %r1, 8(%r2) /* get next pte */ + cmp 0, 0, %r1, %r3 /* see if found pte */ + bdnzf 2, ceq1 /* dec count br if cmp ne and if count not zero */ + bne cEq0SecHash /* if not found set up second hash or exit */ + lwz %r1, +4(%r2) /* load tlb entry lower-word */ + andi. %r3, %r1, 0x80 /* check the C-bit */ + beq cEq0ChkProt /* if (C==0) go check protection modes */ +ceq2: + mtctr %r0 /* restore counter */ + mfspr %r0, SPR_DMISS /* get the miss address for the tlbld */ + mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */ + mtcrf 0x80, %r3 /* restore CR0 */ + mtspr SPR_RPA, %r1 /* set the pte */ + tlbld %r0 /* load the dtlb */ + rfi /* return to executing program */ +/* + * Register usage: + * r0 is saved counter + * r1 is junk + * r2 is pointer to pteg + * r3 is current compare value +*/ + +cEq0SecHash: + andi. %r1, %r3, 0x0040 /* see if we have done second hash */ + bne doDSI /* if so, go to DSI interrupt */ + mfspr %r2, SPR_HASH2 /* get the second pointer */ + ori %r3, %r3, 0x0040 /* change the compare value */ + addi %r1, 0, 8 /* load 8 for counter */ + addi %r2, %r2, -8 /* pre dec for update on load */ + b ceq0 /* try second hash */ + +/* + * entry found and PTE(c-bit==0): + * (check protection before setting PTE(c-bit) + * Register usage: + * r0 is saved counter + * r1 is PTE entry + * r2 is pointer to pteg + * r3 is trashed + */ +cEq0ChkProt: + rlwinm. %r3,%r1,30,0,1 /* test PP */ + bge- chk0 /* if (PP == 00 or PP == 01) goto chk0: */ + andi. %r3, %r1, 1 /* test PP[0] */ + beq+ chk2 /* return if PP[0] == 0 */ + b doDSIp /* else DSIp */ +chk0: + mfspr %r3,SPR_SRR1 /* get old msr */ + andis. %r3,%r3,0x0008 /* test the KEY bit (SRR1-bit 12) */ + beq chk2 /* if (KEY==0) goto chk2: */ + b doDSIp /* else DSIp */ +chk2: + ori %r1, %r1, 0x180 /* set reference and change bit */ + sth %r1, 6(%r2) /* update page table */ + b ceq2 /* and back we go */ + +/* + * entry Not Found: synthesize a DSI interrupt + * Entry: + * r0 is saved counter + * r1 is junk + * r2 is pointer to pteg + * r3 is current compare value + */ +doDSI: + mfspr %r3, SPR_SRR1 /* get srr1 */ + rlwinm %r1,%r3,9,6,6 /* get srr1<flag> to bit 6 for load/store, zero rest */ + addis %r1, %r1, 0x4000 /* or in dsisr<1> = 1 to flag pte not found */ + b dsi1 +doDSIp: + mfspr %r3, SPR_SRR1 /* get srr1 */ + rlwinm %r1,%r3,9,6,6 /* get srr1<flag> to bit 6 for load/store, zero rest */ + addis %r1, %r1, 0x0800 /* or in dsisr<4> = 1 to flag prot violation */ +dsi1: + mtctr %r0 /* restore counter */ + andi. %r2, %r3, 0xffff /* clear upper bits of srr1 */ + mtspr SPR_SRR1, %r2 /* set srr1 */ + mtspr SPR_DSISR, %r1 /* load the dsisr */ + mfspr %r1, SPR_DMISS /* get miss address */ + rlwinm. %r2,%r2,0,31,31 /* test LE bit */ + beq dsi2 /* if little endian then: */ + xor %r1, %r1, 0x07 /* de-mung the data address */ +dsi2: + mtspr SPR_DAR, %r1 /* put in dar */ + mfmsr %r0 /* get msr */ + xoris %r0, %r0, 0x2 /* flip the msr<tgpr> bit */ + mtcrf 0x80, %r3 /* restore CR0 */ + mtmsr %r0 /* flip back to the native gprs */ + ba 0x300 /* branch to DSI interrupt */ + +CNAME(dsmisssize) = .-CNAME(dsmisstrap) + +/* * Similar to the above for DSI * Has to handle BAT spills * and standard pagetable spills --MP_2T7mzsrHA=2RIWRHB2KGn7J--
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