Date: Tue, 9 Mar 2010 21:27:54 +1100 From: Peter Jeremy <peterjeremy@acm.org> To: freebsd-sparc64@freebsd.org Cc: Marius Strobl <marius@alchemy.franken.de> Subject: Re: gcc code generation problems Message-ID: <20100309102753.GC3978@server.vk2pj.dyndns.org> In-Reply-To: <20100308190301.GA69938@server.vk2pj.dyndns.org> References: <20100228192329.GA68252@server.vk2pj.dyndns.org> <20100308190301.GA69938@server.vk2pj.dyndns.org>
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--5QAgd0e35j3NYeGe Content-Type: multipart/mixed; boundary="hQiwHBbRI9kgIhsi" Content-Disposition: inline --hQiwHBbRI9kgIhsi Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On 2010-Mar-09 06:03:01 +1100, Peter Jeremy <peterjeremy@acm.org> wrote: >code works. The "UltraSPARC IIIi Processor User's Manual", indicates >that fxtod will trap for operands >=3D 2^51 (fdtox will trap for >operands >=3D 2^53 and is therefore executed in hardware) which seems to >point the finger at the FP emulation code in the userland trap handler. Attached is a block of assembler that loads all 32 double FP registers with known non-zero values, executes a fxtod and then prints the values of all FP registers. This shows that the register following the emulated fxtod target is incorrectly zeroed. In the attached, the target is %f10 but I've also tried %f8 - which zeroed %f10. The three columns are: FP register number, value before fxtod, value after fxtod. Typical output on my USIIIi: 0 0xfddb757dbd5b7ddf 0xfddb757dbd5b7ddf 2 0xfbb6eafb7ab6fbbf 0xfbb6eafb7ab6fbbf 4 0xf76dd5f6f56df77f 0xf76dd5f6f56df77f 6 0xeedbabedeadbeeff 0xeedbabedeadbeeff 8 0xddb757dbd5b7ddff 0xddb757dbd5b7ddff 10 0xbb6eafb7ab6fbbff 0x432ffffffffffffe 12 0x76dd5f6f56df77ff 0x0000000000000000 14 0x000fffffffffffff 0x000fffffffffffff 16 0xdb757dbd5b7ddffd 0xdb757dbd5b7ddffd 18 0xb6eafb7ab6fbbffb 0xb6eafb7ab6fbbffb 20 0x6dd5f6f56df77ff7 0x6dd5f6f56df77ff7 22 0xdbabedeadbeeffee 0xdbabedeadbeeffee 24 0xb757dbd5b7ddffdd 0xb757dbd5b7ddffdd 26 0x6eafb7ab6fbbffbb 0x6eafb7ab6fbbffbb 28 0xdd5f6f56df77ff76 0xdd5f6f56df77ff76 30 0xbabedeadbeeffeed 0xbabedeadbeeffeed 32 0x757dbd5b7ddffddb 0x757dbd5b7ddffddb 34 0xeafb7ab6fbbffbb6 0xeafb7ab6fbbffbb6 36 0xd5f6f56df77ff76d 0xd5f6f56df77ff76d 38 0xabedeadbeeffeedb 0xabedeadbeeffeedb 40 0x57dbd5b7ddffddb7 0x57dbd5b7ddffddb7 42 0xafb7ab6fbbffbb6e 0xafb7ab6fbbffbb6e 44 0x5f6f56df77ff76dd 0x5f6f56df77ff76dd 46 0xbedeadbeeffeedba 0xbedeadbeeffeedba 48 0x7dbd5b7ddffddb75 0x7dbd5b7ddffddb75 50 0xfb7ab6fbbffbb6ea 0xfb7ab6fbbffbb6ea 52 0xf6f56df77ff76dd5 0xf6f56df77ff76dd5 54 0xedeadbeeffeedbab 0xedeadbeeffeedbab 56 0xdbd5b7ddffddb757 0xdbd5b7ddffddb757 58 0xb7ab6fbbffbb6eaf 0xb7ab6fbbffbb6eaf 60 0x6f56df77ff76dd5f 0x6f56df77ff76dd5f 62 0xdeadbeeffeedbabe 0xdeadbeeffeedbabe >I am still looking into the emulation code. I haven't found the above bug yet but I have found two other bugs in the FP register decoding in __fpu_execute(). Firstly, for fxto{s,d,q} decoding, rs2 is set generically using RN_DECODE() with 'type' =3D=3D 0 (because the low 2 bits are always 0. In this case, RN_DECODE() will assume a 32-bit rs2, whereas the SPARC architecture manual specifies that fxto{s,d,q} has a 64-bit rs2. The effect is that using a source register in the upper half will alias to the lower half. The rd value used in f{s,d,q}tox suffers from the same problem. --=20 Peter Jeremy --hQiwHBbRI9kgIhsi Content-Type: text/plain; charset=us-ascii Content-Disposition: attachment; filename="eval.s" Content-Transfer-Encoding: quoted-printable .file "eval.s" .section ".text" .macro initfp ireg,wreg,wmem,fnum stx \ireg,\wmem ldd \wmem,%f\fnum sllx \ireg,1,\wreg srlx \ireg,63,\ireg or \ireg,\wreg,\ireg .endm .macro savefp wmem,fnum std %f\fnum,[\wmem+4*\fnum] .endm .align 32 .global main .type main, #function .proc 04 main: .register %g2, #scratch .register %g3, #scratch save %sp, -224, %sp ! Initialise all FP registers setx 0xfeedbabedeadbeef,%g1,%g2 setx foo,%g1,%l2 setx bar,%g1,%l3 stx %g2,[%l2] ldd [%l2],%f0 sllx %g2,1,%g1 srlx %g2,63,%g2 or %g2,%g1,%g2 initfp %g2,%g1,[%l2],0 initfp %g2,%g1,[%l2],2 initfp %g2,%g1,[%l2],4 initfp %g2,%g1,[%l2],6 initfp %g2,%g1,[%l2],8 initfp %g2,%g1,[%l2],10 initfp %g2,%g1,[%l2],12 initfp %g2,%g1,[%l2],14 initfp %g2,%g1,[%l2],16 initfp %g2,%g1,[%l2],18 initfp %g2,%g1,[%l2],20 initfp %g2,%g1,[%l2],22 initfp %g2,%g1,[%l2],24 initfp %g2,%g1,[%l2],26 initfp %g2,%g1,[%l2],28 initfp %g2,%g1,[%l2],30 initfp %g2,%g1,[%l2],32 initfp %g2,%g1,[%l2],34 initfp %g2,%g1,[%l2],36 initfp %g2,%g1,[%l2],38 initfp %g2,%g1,[%l2],40 initfp %g2,%g1,[%l2],42 initfp %g2,%g1,[%l2],44 initfp %g2,%g1,[%l2],46 initfp %g2,%g1,[%l2],48 initfp %g2,%g1,[%l2],50 initfp %g2,%g1,[%l2],52 initfp %g2,%g1,[%l2],54 initfp %g2,%g1,[%l2],56 initfp %g2,%g1,[%l2],58 initfp %g2,%g1,[%l2],60 initfp %g2,%g1,[%l2],62 mov 1,%g2 sllx %g2,52,%g2 dec %g2 stx %g2,[%l2] !!! Initialise fxtod source with wanted value ldd [%l2],%f14 ! Save FP regs to memory savefp %l2,0 savefp %l2,2 savefp %l2,4 savefp %l2,6 savefp %l2,8 savefp %l2,10 savefp %l2,12 savefp %l2,14 savefp %l2,16 savefp %l2,18 savefp %l2,20 savefp %l2,22 savefp %l2,24 savefp %l2,26 savefp %l2,28 savefp %l2,30 savefp %l2,32 savefp %l2,34 savefp %l2,36 savefp %l2,38 savefp %l2,40 savefp %l2,42 savefp %l2,44 savefp %l2,46 savefp %l2,48 savefp %l2,50 savefp %l2,52 savefp %l2,54 savefp %l2,56 savefp %l2,58 savefp %l2,60 savefp %l2,62 !!! Do something fxtod %f14,%f10 target: ! Save FP regs to memory after savefp %l3,0 savefp %l3,2 savefp %l3,4 savefp %l3,6 savefp %l3,8 savefp %l3,10 savefp %l3,12 savefp %l3,14 savefp %l3,16 savefp %l3,18 savefp %l3,20 savefp %l3,22 savefp %l3,24 savefp %l3,26 savefp %l3,28 savefp %l3,30 savefp %l3,32 savefp %l3,34 savefp %l3,36 savefp %l3,38 savefp %l3,40 savefp %l3,42 savefp %l3,44 savefp %l3,46 savefp %l3,48 savefp %l3,50 savefp %l3,52 savefp %l3,54 savefp %l3,56 savefp %l3,58 savefp %l3,60 savefp %l3,62 =09 mov 0, %l1 setx .LLC0,%g1,%l0 loop: mov %l0,%o0 ldx [%l2],%o2 ldx [%l3],%o3 call printf,0 mov %l1,%o1 add %l1,2,%l1 add %l3,8,%l3 cmp %l1,64 bne,pt %icc,loop add %l2,8,%l2 =09 call exit, 0 mov 0, %o0 nop .size main,(.-main) .align 8 .section ".rodata1",#alloc .align 8 =2ELLC0: .asciz "%2d 0x%016lx 0x%016lx\n" .type .LLC0,#object .size .LLC0,24 .local foo .common foo,256,8 .local bar .common bar,256,8 .end --hQiwHBbRI9kgIhsi-- --5QAgd0e35j3NYeGe Content-Type: application/pgp-signature Content-Disposition: inline -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.14 (FreeBSD) iEYEARECAAYFAkuWIqkACgkQ/opHv/APuIeE8wCfZzqZD7Hj72KIGMGxflpNPg0p QkUAniLoHon3YIZumV/60LtlGa524lf1 =Mpkc -----END PGP SIGNATURE----- --5QAgd0e35j3NYeGe--
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