Date: Sat, 10 May 2014 18:39:55 +0100 From: Mark R V Murray <markm@FreeBSD.org> To: freebsd-arm <freebsd-arm@freebsd.org> Subject: Fast cycle counter for ARM chips with SCC - patch for review. Message-ID: <22E12094-E6B2-42F9-94AB-014A702D17F2@FreeBSD.org>
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Hi *
This patch makes the ARM6 kernels that have an SCC coprocessor (RPI and =
WANDBOARD have them) get a MUCH better implementation of =
get_cyclecount(9), but not a perfect one. The incrementing rate is good =
(+- 1 per instruction), but its only 32 bits. Later, if there is =
interest, I may wish to fix that with an overflow interrupt, but for now =
its easily good enough for the kernel entropy harvesting service. Also, =
its MUUUCH more efficient; a simple read rather can calling the internal =
kernel binuptime(9) clock.
Comments, please? I=92m keen to commit.
M
--=20
Mark R V Murray
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Index: sys/arm/arm/cpufunc.c
===================================================================
--- sys/arm/arm/cpufunc.c (revision 265841)
+++ sys/arm/arm/cpufunc.c (working copy)
@@ -1387,6 +1387,29 @@
}
#endif /* CPU_ARM9E || CPU_ARM10 */
+#if defined(CPU_ARM1136) || defined(CPU_ARM1176) \
+ || defined(CPU_MV_PJ4B) \
+ || defined(CPU_CORTEXA) || defined(CPU_KRAIT)
+static __inline void
+cpu_scc_setup_ccnt(void)
+{
+ /* Set up the PMCCNTR register as a cyclecounter:
+ * Set PMUSERENR[0] to 1 to allow user read
+ * Set PMINTENCLR to 0x8000000F to block interrupts
+ * Set PMCR[0] to 1 to enable CCNT
+ * Set PMCNTENSET to 0x8000000F to enable counters */
+ __asm volatile ("mcr p15, 0, %0, c9, c14, 0\n\t"
+ "mcr p15, 0, %1, c9, c14, 2\n\t"
+ "mcr p15, 0, %2, c9, c12, 0\n\t"
+ "mcr p15, 0, %3, c9, c12, 1\n\t"
+ :
+ : "r"(0x00000001),
+ "r"(0x8000000F),
+ "r"(0x00000007),
+ "r"(0x8000000F));
+}
+#endif
+
#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
struct cpu_option arm11_options[] = {
{ "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
@@ -1490,6 +1513,8 @@
/* And again. */
cpu_idcache_wbinv_all();
+
+ cpu_scc_setup_ccnt();
}
#endif /* CPU_ARM1136 || CPU_ARM1176 */
@@ -1524,6 +1549,8 @@
/* And again. */
cpu_idcache_wbinv_all();
+
+ cpu_scc_setup_ccnt();
}
#endif /* CPU_MV_PJ4B */
@@ -1571,6 +1598,8 @@
#ifdef SMP
armv7_auxctrl((1 << 6) | (1 << 0), (1 << 6) | (1 << 0)); /* Enable SMP + TLB broadcasting */
#endif
+
+ cpu_scc_setup_ccnt();
}
#endif /* CPU_CORTEXA */
Index: sys/arm/include/cpu.h
===================================================================
--- sys/arm/include/cpu.h (revision 265841)
+++ sys/arm/include/cpu.h (working copy)
@@ -14,11 +14,26 @@
static __inline uint64_t
get_cyclecount(void)
{
+/* This '#if' asks the question 'Do we have a System Control Coprocessor?' */
+#if defined(CPU_ARM1136) || defined(CPU_ARM1176) \
+ || defined(CPU_MV_PJ4B) \
+ || defined(CPU_CORTEXA) || defined(CPU_KRAIT)
+ uint32_t ccnt;
+ uint64_t ccnt64;
+
+ /*
+ * Read PMCCNTR. Curses! Its only 32 bits.
+ * TODO: Fix this by catching overflow with interrupt?
+ */
+ __asm __volatile("mrc p15, 0, %0, c9, c13, 0": "=r" (ccnt));
+ ccnt64 = (uint64_t)ccnt;
+ return (ccnt64);
+#else /* No SCC, use binuptime(9). This is slooooow */
struct bintime bt;
binuptime(&bt);
return ((uint64_t)bt.sec << 56 | bt.frac >> 8);
-
+#endif
}
#endif
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Content-Transfer-Encoding: 7bit
Content-Disposition: attachment;
filename=signature.asc
Content-Type: application/pgp-signature;
name=signature.asc
Content-Description: Message signed with OpenPGP using GPGMail
-----BEGIN PGP SIGNATURE-----
Version: GnuPG/MacGPG2 v2.0.22 (Darwin)
Comment: GPGTools - http://gpgtools.org
iQCVAwUBU25kb958vKOKE6LNAQrk+wP+PmL6xGV284KMuynxLtUOt27mVoJaefBP
Bc3KinklrFEmy25XDszy8JXYB9G/0mzJTSFy5KUL+2w5+4i9JJcnGYqvQSSoAR0o
J+0CBtaLq1iGWDa+uDrLx66D2WwHIFnozgOxGfSvpUnlLmm3gMe4iPOxkFB5jwnI
gwcq2Zp6+VM=
=fJWB
-----END PGP SIGNATURE-----
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