Date: Sat, 01 Feb 2003 13:06:47 -0800 From: Terry Lambert <tlambert2@mindspring.com> To: Matthew Dillon <dillon@apollo.backplane.com> Cc: "Kurt J. Lidl" <lidl@pix.net>, Mats Larsson <myrslok@marvin.sko.mh.se>, hackers@FreeBSD.ORG Subject: Re: Lower power SMP boxes? Message-ID: <3E3C36E7.1A77AABA@mindspring.com> References: <200301312312.h0VNC5bQ007170@apollo.backplane.com> <20030201101041.H16130@marvin.sko.mh.se> <20030201123303.A6376@pix.net> <200302011921.h11JLnrk016623@apollo.backplane.com>
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Matthew Dillon wrote: > :It says "IO/APIC support in future versions". So, it's not an SMP option > :today, as I understand it. > > Although, this is more a deficiency in the way FreeBSD is designed. Using > an APIC is nice, but not absolutely necessary. All we need are good > specs on how VIA's SMP cpus interact with each other and we could > support it. You mean FreeBSD's requirement that Intel-based motherboards comply with the Intel Multiprocessing specification is a deficiency in FreeBSD? 8-). The best you can get is to modify the MMU and/or replace the L2 cache with hardware that performs negotiations. Even then, the coherency model would have to move from MESI, which is how it operates in the presence of an APIC, to MEI, instead, a *very significant* change, particularly for locking, which would require explicit signalling for synchronization. MEI is the model used by the BeBox and other PPC multiprocessors that were never intended to be SMP-ized: the PPC 601 and PPC 603 processors were never intended to be used in an SMP configuration, FWIW. > I like the 11 watts specified in the paper. That *is* low power for > the class of system they are selling. I don't see a clock specification > but I assume it is going to be at least as fast as the ~900MHz M-9000. The easiest thing to do is under-clock a very fast processor, if what you want to do is drop power requirements, as you've said. Running at a lower clock multiplier has other significant advantages, as well, since the interprocessor communication imposes a stall barrier in the arbitration logic (whether it's MESI, or MEI), so the closer the CPU is to the arbitration logic speed, the less the multiplier amplifies stalls into empty instruction pipelines. I'm pretty sure that Intel no longer sells the external APIC chips that used to be used to make 486 SMP systems that complied with the Intel MP Specification (the 486 never had an internal APIC, either), but that might also be an option. Were that the path taken, then there would be no serious changes required in FreeBSD (except perhaps the need to support MP Spec. 1.1 as well as 1.4, and FreeBSD did that successfully in the past). -- Terry To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-hackers" in the body of the message
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