Date: Wed, 25 Jan 2006 08:04:07 -0700 From: Scott Long <scottl@samsco.org> To: Craig Boston <craig@tobuj.gank.org> Cc: freebsd-hackers@freebsd.org Subject: Re: Weird PCI interrupt delivery problem (resolution, sort of) Message-ID: <43D79367.6020304@samsco.org> In-Reply-To: <200601250916.59336.jhb@freebsd.org> References: <20060120014307.GA3118@nowhere> <200601241043.51094.jhb@freebsd.org> <20060125003405.GA29970@nowhere> <200601250916.59336.jhb@freebsd.org>
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John Baldwin wrote: > On Tuesday 24 January 2006 19:34, Craig Boston wrote: > >>On Tue, Jan 24, 2006 at 10:43:49AM -0500, John Baldwin wrote: >> >>>What if you do a read of the lapic before the write? Maybe doing 'x = >>>lapic->eoi; lapic->eoi = 0;'? >> >>Reading the lapic before the write has no effect. >> >>Reading the lapic after the write makes it work. > > > Hmm, perhaps the read forces the write to post? Scott? > Either that, or the read imposes enough delay to let whatever was happening during the DELAY call work. I find it hard to believe that uncached writes would get delayed like this. I've lost the original posting on this, could you provide the dmesg and computer make/model again? Scott
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