Date: Thu, 05 Aug 2010 01:13:47 -0500 From: Alan Cox <alc@cs.rice.edu> To: "Jayachandran C." <jchandra@FreeBSD.org> Cc: mips@freebsd.org Subject: Re: svn commit: r210846 - in head/sys/mips: include mips Message-ID: <4C5A569B.9090401@cs.rice.edu> In-Reply-To: <201008041412.o74ECAix092415@svn.freebsd.org> References: <201008041412.o74ECAix092415@svn.freebsd.org>
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Just an observation ... Jayachandran C. wrote: > Author: jchandra > Date: Wed Aug 4 14:12:09 2010 > New Revision: 210846 > URL: http://svn.freebsd.org/changeset/base/210846 > > Log: > Add 3 level page tables for MIPS in n64. > > - 32 bit compilation will still use old 2 level page tables > - re-arrange pmap code so that adding another level is easier > - pmap code for 3 level page tables for n64 > - update TLB handler to traverse 3 levels in n64 > > Reviewed by: jmallett > [snip] > > - if (pbits != *pte) { > - if (!atomic_cmpset_int((u_int *)pte, obits, pbits)) > - goto retry; > - pmap_update_page(pmap, sva, pbits); > + /* Skip invalid PTEs */ > + if (!pte_test(pte, PTE_V)) > + continue; > +retry: > + obits = pbits = *pte; > + pa = TLBLO_PTE_TO_PA(pbits); > + if (page_is_managed(pa) && pte_test(&pbits, PTE_D)) { > + m = PHYS_TO_VM_PAGE(pa); > + vm_page_dirty(m); > + m->md.pv_flags &= ~PV_TABLE_MOD; > + } > + pte_clear(&pbits, PTE_D); > + pte_set(&pbits, PTE_RO); > + > + if (pbits != *pte) { > + if (!atomic_cmpset_int((u_int *)pte, obits, pbits)) > + goto retry; > + pmap_update_page(pmap, sva, pbits); > + } > } > MIPS doesn't really need to use atomic_cmpset_int() in situations like this because the software dirty bit emulation in trap.c acquires the pmap lock. Atomics like this appear to be a carryover from i386 where the hardware-managed TLB might concurrently set the modified bit.
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