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Date:      Sun, 25 Jun 2017 16:53:43 -0500
From:      "A. Wilcox" <AWilcox@Wilcox-Tech.com>
To:        freebsd-current@freebsd.org
Subject:   Re: Skylake/Kabylake Intel Bug?
Message-ID:  <595030E7.1030400@Wilcox-Tech.com>
In-Reply-To: <a5e8f4c4-9cbb-d229-12a7-ce9c21bfe832@nomadlogic.org>
References:  <a5e8f4c4-9cbb-d229-12a7-ce9c21bfe832@nomadlogic.org>

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On 25/06/17 12:56, Pete Wright wrote:
> Came across this post today via HN regarding a issue with Hyperthreadin=
g
> causing unpredictable behavior on these CPU's
>=20
> https://lists.debian.org/debian-devel/2017/06/msg00308.html
>=20
> I really wish there was more info on this in the email, for example
> examples of programs being effected by this bug.  Anywho - was wonderin=
g
> if any devs here had more info on this issue and could provide better
> context?
>=20
> Cheers,
>=20
> -pete
>=20

The linked OCaml issue goes quite in-depth with the mechanisms behind
this bug and the risks behind not patching the microcode:

https://caml.inria.fr/mantis/view.php?id=3D7452


Basically, if a HyperThreaded core is running a tight loop accessing
%rax and %ah (or %rbx and %bh, etc) in quick succession, on both threads
of the same physical core, it can corrupt/poison L1d cache.

AIUI, OCaml manages to generate this code by manipulating tagged memory
addresses and the corresponding tag (the address is in %rax, and the tag
is at %ah).

I'd really love to see if this affects write-through-no-allocate cache
or only write-behind, but I haven't seen any program besides OCaml
actually manage to get GCC to generate the insn pattern that is needed,
and I don't have a Skylake or Kaby Lake CPU to test with anyway.


Fun little hardware bug.


Hope this helps you,
--arw

--=20
A. Wilcox (awilfox)
Open-source programmer (C, C++, Python)
https://code.foxkit.us/u/awilfox/


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