Date: Mon, 19 May 2008 10:18:29 -0700 From: "Jerry Toung" <jrytoung@gmail.com> To: freebsd-mips@freebsd.org Subject: freebsd on mips64 Message-ID: <86068e730805191018l3a6feedal1d47fd77f5b50f72@mail.gmail.com>
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Hello List, The company I work for is very interested in moving from FreeBSD/x86 to MIPS. To start, we are planning on getting an evaluation board from either RAZA microelectronics with an XLR processor (MIPS64) or from Cavium with an OCTEON (MIPS64). I understand that the FreeBSD/mips port is still under development. Because we are motivated, I would like to join the project and help as much as I can. I went to http://wiki.freebsd.org/FreeBSD/mips and got the snapshot from August 10, 2007 and also installed gxemul (GXemul 0.4.2) from the ports of my 6.2 machine. I wasn't able to retrieve gonzo's patches at http://gonzo.kiev.ua/mips/freebsd-gxemul-0.4.1.patch as per src/EMULATION 1- Please look at the pasted output at the bottom of the email and advise on what's wrong so I can boot to single user mode or to where ever you guys are now. 2- Based on my requirements above (xlr or octeon), could you advise on where I should start/what I will need for this port so I can get up to speed and contribute? (i.e docs, books, current source code, etc) 3- what is the current road map? what's on the TODO list as of now. I am sure I'll have more questions as we move forward. Thank you for listening. Jerry jtoung : gxemul -Vv -e malta -C 4kc -d /dev/null /usr/home/jtoung/FreeBSD/mips.build/mips/usr/home/jtoung/src/sys/MALTA/kernel GXemul 0.4.2 Copyright (C) 2003-2006 Anders Gavare Read the source code and/or documentation for other Copyright messages. Simple setup... net: simulating 10.0.0.0/8 (max outgoing: TCP=100, UDP=100) simulated gateway: 10.0.0.254 (60:50:40:30:20:10) using nameserver 10.10.10.10 machine "default": memory: 64 MB cpu0: 4Kc (I+D = 16+16 KB) machine: MALTA (evbmips, little endian) bootstring: kernel diskimage: /dev/null IDE DISK id 0, read/write, 0 MB (0 sectors) loading /usr/home/jtoung/FreeBSD/mips.build/mips/usr/home/jtoung/src/sys/MALTA/kernel starting cpu0 at 0x801292f0 (gp=0x80355140) ------------------------------------------------------------------------------- GXemul> c [ ns16550 (tty0): read from iir: 0x01 ] [ ns16550 (tty0): read from mcr: 0x00 ] [ ns16550 (tty0): write to lctl: 0x83 (Divisor Latch access, setting mode 8N1) ] [ ns16550 (tty0): speed set to 115200 bps ] [ ns16550 (tty0): write to lctl: 0x03 (setting mode 8N1) ] [ ns16550 (tty0): write to fifo control: 0x00 ] [ ns16550 (tty0): write to mcr: 0x0b ] [ ns16550 (tty0): read from iir: 0x03 ] entry: mips_init() picache_stride = 4096 picache_loopcount = 4 pdcache_stride = 4096 pdcache_loopcount = 4 Installing exception vector: [0x80000000..0x80000080] <- [0x802efc18..0x802efc94] Exception vector at 80000000 almost out of space Installing exception vector: [0x80000080..0x80000100] <- [0x802efd08..0x802efd20] Installing exception vector: [0x80000100..0x80000180] <- [0x802efb3c..0x802efb54] Installing exception vector: [0x80000200..0x80000280] <- [0x802efa60..0x802efa98] Installing exception vector: [0x80000180..0x80000200] <- [0x802efa60..0x802efa98] Physical memory chunk(s): 0x35e2b0 - 0xffffff, 13245776 bytes (3233 pages) Kernel page table maps 4096 4K pages and is 511K [ yamon_emul(): syscon: TODO ] MIPS32 clock: 100000000 Hz Copyright (c) 1992-2007 The FreeBSD Project. Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994 The Regents of the University of California. All rights reserved. FreeBSD is a registered trademark of The FreeBSD Foundation. FreeBSD 7.0-CURRENT #0: Fri May 16 15:32:46 PDT 2008 jtoung@jtoung-bsd. :/usr/home/jtoung/FreeBSD/mips.build/mips/usr/home/jtoung/src/sys/MALTA [ exception TLBS <tlb> vaddr=0xe0000000 pc=0x802f478c ] [ exception TLBS <tlb> vaddr=0xe0002000 pc=0x802f478c ] [ exception TLBS <tlb> vaddr=0xe0004000 pc=0x802f478c ] [ exception TLBS <tlb> vaddr=0xe0006000 pc=0x802f478c ] [ exception TLBS <tlb> vaddr=0xe0008000 pc=0x802f478c ] ............................................................................................................... [ exception TLBS <tlb> vaddr=0xe0000010 pc=0x802cd53c <uma_startup+0xf8> ] [ exception TLBS <tlb> vaddr=0xe0004010 pc=0x802cd53c <uma_startup+0xf8> ] [ exception TLBS <tlb> vaddr=0xe0006010 pc=0x802cd53c <uma_startup+0xf8> ] [ exception TLBS <tlb> vaddr=0xe000e010 pc=0x802cd53c <uma_startup+0xf8> ] ....................................................................................................................... [ exception TLBS <tlb> vaddr=0xe006c000 pc=0x802f478c ] [ exception TLBS <tlb> vaddr=0xe003103c pc=0x802e1600 <vm_page_startup+0x238> ] [ exception TLBS <tlb> vaddr=0xe003202c pc=0x802e1600 <vm_page_startup+0x238> ] [ exception TLBS <tlb> vaddr=0xe003400c pc=0x802e1600 <vm_page_startup+0x238> ]
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