Date: Thu, 31 Mar 2011 17:09:05 -0400 From: Arnaud Lacombe <lacombar@gmail.com> To: Jack Vogel <jfvogel@gmail.com> Cc: freebsd-net@freebsd.org Subject: Re: em(4) hang [Was: Re: igb(4) won't start with "igb0: Could not setup receive structures"] Message-ID: <AANLkTi=OjzMrjCPZ2VFDBf6URTaMoAzQqXbxWLv3d9mW@mail.gmail.com> In-Reply-To: <AANLkTin64gGxRituE2B%2BsfVpRXt2QetdNLaV7HCf0uNE@mail.gmail.com> References: <AANLkTin64gGxRituE2B%2BsfVpRXt2QetdNLaV7HCf0uNE@mail.gmail.com>
next in thread | previous in thread | raw e-mail | index | archive | help
Hi Jack, On Thu, Mar 31, 2011 at 9:51 AM, Arnaud Lacombe <lacombar@gmail.com> wrote: > [...] > I'll remove part of the changes I made to keep only `rx_forced_refill' > and the associated sysctl, re-run the tests and come back with correct > value, hopefully in a few hours. > Here it is: # sysctl dev.em.0.%desc dev.em.0.%desc: Intel(R) PRO/1000 Network Connection 7.2.2 # sysctl dev.em.0.mac_stats.missed_packets dev.em.0.mac_stats.missed_packets: 917428 # sysctl dev.em.0.debug=3D1 dev.em.0.debug: I-1nterface is RUNNING and INACTIVE em0: hw tdh =3D 975, hw tdt =3D 975 em0: hw rdh =3D 884, hw rdt =3D 885 em0: Tx Queue Status =3D 0 em0: TX descriptors avail =3D 1024 em0: Tx Descriptors avail failure =3D 0 em0: RX discarded packets =3D 0 em0: RX Next to Check =3D 884 em0: RX Next to Refresh =3D 885 -> -1 So the taskqueue cannot be scheduled to run and the driver is stuck. > On Wed, Mar 30, 2011 at 2:22 PM, Jack Vogel <jfvogel@gmail.com> wrote: >> Read the code in HEAD, em_local_timer() has a test of ALL the rx queues = and >> will schedule a task that refreshes mbufs if they are empty. This has >> exactly the >> same effect as checking for some interrupt cause, a cause that is not >> available >> when using MSIX on 82574, but this approach works for everything. >> Can you please point me to a reference datasheet (or errata), provided by Intel, about the RX Overrun interrupt not being available with MSI-X on the 82574 ? Currently, I only have access to [0], which precises the following: 7.4 Interrupts 7.4.2 MSI-X Mode [...] The following configuration and parameters are involved: =95 The IVAR.INT_Alloc[4:0] entries map two Tx queues, two Rx queues and ot= her events to 5 interrupt vectors =95 The ICR[24:20] bits reflect specific interrupt causes =95 Five MSI-X interrupt vectors are provided (calculated based on four vectors for queues and one vector for other causes). The requested number of vectors is loaded from the MSI_X_N fields in the EEPROM into the PCIe MSI-X capability structure of the function. 10.2.4.1 Interrupt Cause Read Register - ICR (0x000C0; RC/WC) [...] about bit 24: Other Interrupt. Indicates one of the following interrupts was set: =95 Link Status Change. =95 Receiver Overrun. =95 MDIO Access Complete. =95 Small Receive Packet Detected. =95 Receive ACK Frame Detected. =95 Manageability Event Detected. Thanks in advance, - Arnaud [0]: ftp://download.intel.com/design/network/datashts/82574.pdf
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?AANLkTi=OjzMrjCPZ2VFDBf6URTaMoAzQqXbxWLv3d9mW>