Date: Mon, 21 Jun 2010 22:18:50 +0530 From: "Jayachandran C." <c.jayachandran@gmail.com> To: Randall Stewart <rrs@lakerest.net>, Juli Mallett <jmallett@freebsd.org>, "M. Warner Losh" <imp@bsdimp.com>, freebsd-mips@freebsd.org Subject: Re: Merging 64 bit changes to -HEAD - part 3 Message-ID: <AANLkTim5aGluEVgYQQxgBDn2aJIuUIIMszmk7D3lVEGi@mail.gmail.com>
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[-- Attachment #1 --] On Tue, Jun 15, 2010 at 7:06 PM, Jayachandran C. <c.jayachandran@gmail.com> wrote: > I have volunteered to merge Juli's 64-bit work into HEAD, and > hopefully get it to work on XLR too. The tree > (http://svn.freebsd.org/base/user/jmallett/octeon) has quite a bit of > changes, so I would like to do this over multiple changesets and > without breaking the current o32 code. And here's the third batch for the merge, two patches here: n64-n32-compile.patch: Main changes are: - Support for n64 and n32 kernel compilation - casts between registers and ptr/int updated to work on 64bit - 64-bit address space defines - syscall, exception and trap support for n32/n64 I have made some minor changes from the Juli's version to reduce the number of #ifdefs, but mostly the code is equivalent. n32-kernel.patch: - Support to build n32 kernel for XLR, sample conf file and ldscript With these two patches the kernel comes up in n32 single user mode. Please let me know your comments. The next set should cover the full n64 support. Thanks, JC. [-- Attachment #2 --] Index: sys/mips/include/setjmp.h =================================================================== --- sys/mips/include/setjmp.h (revision 209367) +++ sys/mips/include/setjmp.h (working copy) @@ -39,7 +39,7 @@ #include <sys/cdefs.h> -#define _JBLEN 95 /* size, in longs, of a jmp_buf */ +#define _JBLEN 95 /* size, in longs (or long longs), of a jmp_buf */ /* * jmp_buf and sigjmp_buf are encapsulated in different structs to force @@ -49,10 +49,18 @@ #ifndef _LOCORE #ifndef __ASSEMBLER__ #if __BSD_VISIBLE || __POSIX_VISIBLE || __XSI_VISIBLE +#ifdef __mips_n32 +typedef struct _sigjmp_buf { long long _sjb[_JBLEN + 1]; } sigjmp_buf[1]; +#else typedef struct _sigjmp_buf { long _sjb[_JBLEN + 1]; } sigjmp_buf[1]; #endif +#endif +#ifdef __mips_n32 +typedef struct _jmp_buf { long long _jb[_JBLEN + 1]; } jmp_buf[1]; +#else typedef struct _jmp_buf { long _jb[_JBLEN + 1]; } jmp_buf[1]; +#endif #endif /* __ASSEMBLER__ */ #endif /* _LOCORE */ Index: sys/mips/include/cpu.h =================================================================== --- sys/mips/include/cpu.h (revision 209367) +++ sys/mips/include/cpu.h (working copy) @@ -49,7 +49,7 @@ #include <machine/endian.h> -#define MIPS_KSEG0_LARGEST_PHYS 0x20000000 +#define MIPS_KSEG0_LARGEST_PHYS (0x20000000) #define MIPS_PHYS_MASK (0x1fffffff) #define MIPS_PHYS_TO_KSEG0(x) ((uintptr_t)(x) | MIPS_KSEG0_START) @@ -162,11 +162,11 @@ /* * Location of exception vectors. */ -#define RESET_EXC_VEC 0xbfc00000 -#define TLB_MISS_EXC_VEC 0x80000000 -#define XTLB_MISS_EXC_VEC 0x80000080 -#define CACHE_ERR_EXC_VEC 0x80000100 -#define GEN_EXC_VEC 0x80000180 +#define RESET_EXC_VEC ((intptr_t)(int32_t)0xbfc00000) +#define TLB_MISS_EXC_VEC ((intptr_t)(int32_t)0x80000000) +#define XTLB_MISS_EXC_VEC ((intptr_t)(int32_t)0x80000080) +#define CACHE_ERR_EXC_VEC ((intptr_t)(int32_t)0x80000100) +#define GEN_EXC_VEC ((intptr_t)(int32_t)0x80000180) /* * Coprocessor 0 registers: Index: sys/mips/include/vmparam.h =================================================================== --- sys/mips/include/vmparam.h (revision 209367) +++ sys/mips/include/vmparam.h (working copy) @@ -100,11 +100,17 @@ #define VM_MAX_ADDRESS ((vm_offset_t)(intptr_t)(int32_t)0xffffffff) #define VM_MINUSER_ADDRESS ((vm_offset_t)0x00000000) -#define VM_MAXUSER_ADDRESS ((vm_offset_t)0x80000000) #define VM_MAX_MMAP_ADDR VM_MAXUSER_ADDRESS -#define VM_MIN_KERNEL_ADDRESS ((vm_offset_t)0xC0000000) -#define VM_MAX_KERNEL_ADDRESS ((vm_offset_t)0xFFFFC000) +#if defined(__mips_n64) +#define VM_MAXUSER_ADDRESS (VM_MINUSER_ADDRESS + (NPDEPG * NPTEPG * PAGE_SIZE)) +#define VM_MIN_KERNEL_ADDRESS ((vm_offset_t)0xc000000000000000) +#define VM_MAX_KERNEL_ADDRESS (VM_MIN_KERNEL_ADDRESS + (NPDEPG * NPTEPG * PAGE_SIZE)) +#else +#define VM_MAXUSER_ADDRESS ((vm_offset_t)0x80000000) +#define VM_MIN_KERNEL_ADDRESS ((vm_offset_t)0xC0000000) +#define VM_MAX_KERNEL_ADDRESS ((vm_offset_t)0xFFFFC000) +#endif #if 0 #define KERNBASE (VM_MIN_KERNEL_ADDRESS) #else Index: sys/mips/mips/vm_machdep.c =================================================================== --- sys/mips/mips/vm_machdep.c (revision 209367) +++ sys/mips/mips/vm_machdep.c (working copy) @@ -141,13 +141,13 @@ if (td1 == PCPU_GET(fpcurthread)) MipsSaveCurFPState(td1); - pcb2->pcb_context[PCB_REG_RA] = (register_t)fork_trampoline; + pcb2->pcb_context[PCB_REG_RA] = (register_t)(intptr_t)fork_trampoline; /* Make sp 64-bit aligned */ pcb2->pcb_context[PCB_REG_SP] = (register_t)(((vm_offset_t)td2->td_pcb & ~(sizeof(__int64_t) - 1)) - CALLFRAME_SIZ); - pcb2->pcb_context[PCB_REG_S0] = (register_t)fork_return; - pcb2->pcb_context[PCB_REG_S1] = (register_t)td2; - pcb2->pcb_context[PCB_REG_S2] = (register_t)td2->td_frame; + pcb2->pcb_context[PCB_REG_S0] = (register_t)(intptr_t)fork_return; + pcb2->pcb_context[PCB_REG_S1] = (register_t)(intptr_t)td2; + pcb2->pcb_context[PCB_REG_S2] = (register_t)(intptr_t)td2->td_frame; pcb2->pcb_context[PCB_REG_SR] = SR_INT_MASK & mips_rd_status(); /* * FREEBSD_DEVELOPERS_FIXME: @@ -178,8 +178,8 @@ * Note that the trap frame follows the args, so the function * is really called like this: func(arg, frame); */ - td->td_pcb->pcb_context[PCB_REG_S0] = (register_t) func; - td->td_pcb->pcb_context[PCB_REG_S1] = (register_t) arg; + td->td_pcb->pcb_context[PCB_REG_S0] = (register_t)(intptr_t)func; + td->td_pcb->pcb_context[PCB_REG_S1] = (register_t)(intptr_t)arg; } void @@ -254,11 +254,18 @@ code = locr0->v0; quad_syscall = 0; +#if defined(__mips_o32) + if (code == SYS___syscall) + quad_syscall = 1; +#endif + if (code == SYS_syscall) code = locr0->a0; else if (code == SYS___syscall) { - code = _QUAD_LOWWORD ? locr0->a1 : locr0->a0; - quad_syscall = 1; + if (quad_syscall) + code = _QUAD_LOWWORD ? locr0->a1 : locr0->a0; + else + code = locr0->a0; } switch (error) { @@ -336,13 +343,13 @@ * Set registers for trampoline to user mode. */ - pcb2->pcb_context[PCB_REG_RA] = (register_t)fork_trampoline; + pcb2->pcb_context[PCB_REG_RA] = (register_t)(intptr_t)fork_trampoline; /* Make sp 64-bit aligned */ pcb2->pcb_context[PCB_REG_SP] = (register_t)(((vm_offset_t)td->td_pcb & ~(sizeof(__int64_t) - 1)) - CALLFRAME_SIZ); - pcb2->pcb_context[PCB_REG_S0] = (register_t)fork_return; - pcb2->pcb_context[PCB_REG_S1] = (register_t)td; - pcb2->pcb_context[PCB_REG_S2] = (register_t)td->td_frame; + pcb2->pcb_context[PCB_REG_S0] = (register_t)(intptr_t)fork_return; + pcb2->pcb_context[PCB_REG_S1] = (register_t)(intptr_t)td; + pcb2->pcb_context[PCB_REG_S2] = (register_t)(intptr_t)td->td_frame; /* Dont set IE bit in SR. sched lock release will take care of it */ pcb2->pcb_context[PCB_REG_SR] = SR_INT_MASK & mips_rd_status(); @@ -385,7 +392,7 @@ * byte aligned[for compatibility with 64-bit CPUs] * in ``See MIPS Run'' by D. Sweetman, p. 269 * align stack */ - sp = ((register_t)(stack->ss_sp + stack->ss_size) & ~0x7) - + sp = ((register_t)(intptr_t)(stack->ss_sp + stack->ss_size) & ~0x7) - CALLFRAME_SIZ; /* @@ -394,14 +401,14 @@ */ tf = td->td_frame; bzero(tf, sizeof(struct trapframe)); - tf->sp = (register_t)sp; - tf->pc = (register_t)entry; + tf->sp = sp; + tf->pc = (register_t)(intptr_t)entry; /* * MIPS ABI requires T9 to be the same as PC * in subroutine entry point */ - tf->t9 = (register_t)entry; - tf->a0 = (register_t)arg; + tf->t9 = (register_t)(intptr_t)entry; + tf->a0 = (register_t)(intptr_t)arg; /* * Keep interrupt mask @@ -409,7 +416,7 @@ tf->sr = SR_KSU_USER | SR_EXL | (SR_INT_MASK & mips_rd_status()) | MIPS_SR_INT_IE; #ifdef TARGET_OCTEON - tf->sr |= MIPS_SR_INT_IE | MIPS_SR_COP_0_BIT | MIPS_SR_UX | + tf->sr |= MIPS_SR_INT_IE | MIPS_SR_COP_0_BIT | MIPS32_SR_PX | MIPS_SR_UX | MIPS_SR_KX; #endif /* tf->sr |= (ALL_INT_MASK & idle_mask) | SR_INT_ENAB; */ @@ -431,7 +438,7 @@ va = pmap_kextract((vm_offset_t)addr); if (va == 0) panic("kvtop: zero page frame"); - return((int)va); + return((intptr_t)va); } /* @@ -547,10 +554,10 @@ #include <ddb/ddb.h> #define DB_PRINT_REG(ptr, regname) \ - db_printf(" %-12s 0x%lx\n", #regname, (long)((ptr)->regname)) + db_printf(" %-12s %p\n", #regname, (void *)(intptr_t)((ptr)->regname)) #define DB_PRINT_REG_ARRAY(ptr, arrname, regname) \ - db_printf(" %-12s 0x%lx\n", #regname, (long)((ptr)->arrname[regname])) + db_printf(" %-12s %p\n", #regname, (void *)(intptr_t)((ptr)->arrname[regname])) static void dump_trapframe(struct trapframe *trapframe) Index: sys/mips/mips/exception.S =================================================================== --- sys/mips/mips/exception.S (revision 209367) +++ sys/mips/mips/exception.S (working copy) @@ -89,6 +89,15 @@ #define ITLBNOPFIX nop;nop;nop;nop;nop;nop;nop;nop;nop;nop; #define HAZARD_DELAY nop;nop;nop;nop;nop; +/* Pointer size and mask for n64 */ +#if defined(__mips_n64) +#define PTRSHIFT 3 +#define PTRMASK 0xff8 +#else +#define PTRSHIFT 2 +#define PTRMASK 0xffc +#endif + /* *---------------------------------------------------------------------------- * @@ -126,12 +135,12 @@ .set noat MipsDoTLBMiss: bltz k0, 1f #02: k0<0 -> 1f (kernel fault) - PTR_SRL k0, k0, SEGSHIFT - 2 #03: k0=seg offset (almost) + PTR_SRL k0, k0, SEGSHIFT - PTRSHIFT #03: k0=seg offset (almost) GET_CPU_PCPU(k1) PTR_L k1, PC_SEGBASE(k1) beqz k1, 2f #05: make sure segbase is not null - andi k0, k0, 0xffc #06: k0=seg offset (mask 0x3) + andi k0, k0, PTRMASK #06: k0=seg offset PTR_ADDU k1, k0, k1 #07: k1=seg entry address PTR_L k1, 0(k1) #08: k1=seg entry @@ -175,6 +184,9 @@ sll k0, k0, 3 # shift user bit for cause index and k1, k1, CR_EXC_CODE # Mask out the cause bits. or k1, k1, k0 # change index to user table +#if defined(__mips_n64) + PTR_SLL k1, k1, 1 # shift to get 8-byte offset +#endif 1: PTR_LA k0, _C_LABEL(machExceptionTable) # get base of the jump table PTR_ADDU k0, k0, k1 # Get the address of the @@ -798,9 +810,9 @@ beqz k1, 3f nop - PTR_SRL k0, SEGSHIFT - 2 # k0=seg offset (almost) + PTR_SRL k0, SEGSHIFT - PTRSHIFT # k0=seg offset (almost) beq k1, zero, MipsKernGenException # ==0 -- no seg tab - andi k0, k0, 0xffc # k0=seg offset (mask 0x3) + andi k0, k0, PTRMASK # k0=seg offset PTR_ADDU k1, k0, k1 # k1=seg entry address PTR_L k1, 0(k1) # k1=seg entry @@ -960,10 +972,10 @@ sltu k1, k1, k0 # upper bound of kernel_segmap bnez k1, MipsKernGenException # out of bound lui k1, %hi(kernel_segmap) # k1=hi of segbase - PTR_SRL k0, SEGSHIFT - 2 # k0=seg offset (almost) + PTR_SRL k0, SEGSHIFT - PTRSHIFT # k0=seg offset (almost) PTR_L k1, %lo(kernel_segmap)(k1) # k1=segment tab base beq k1, zero, MipsKernGenException # ==0 -- no seg tab - andi k0, k0, 0xffc # k0=seg offset (mask 0x3) + andi k0, k0, PTRMASK # k0=seg offset PTR_ADDU k1, k0, k1 # k1=seg entry address PTR_L k1, 0(k1) # k1=seg entry MFC0 k0, COP_0_BAD_VADDR # k0=bad address (again) Index: sys/mips/mips/stack_machdep.c =================================================================== --- sys/mips/mips/stack_machdep.c (revision 209367) +++ sys/mips/mips/stack_machdep.c (working copy) @@ -43,7 +43,7 @@ stack_register_fetch(u_register_t sp, u_register_t stack_pos) { u_register_t * stack = - ((u_register_t *)sp + stack_pos/sizeof(u_register_t)); + ((u_register_t *)(intptr_t)sp + (size_t)stack_pos/sizeof(u_register_t)); return *stack; } @@ -59,19 +59,22 @@ for (;;) { stacksize = 0; - if (pc <= (u_register_t)btext) + if (pc <= (u_register_t)(intptr_t)btext) break; - for (i = pc; i >= (u_register_t)btext; i -= sizeof (insn)) { - bcopy((void *)i, &insn, sizeof insn); + for (i = pc; i >= (u_register_t)(intptr_t)btext; i -= sizeof (insn)) { + bcopy((void *)(intptr_t)i, &insn, sizeof insn); switch (insn.IType.op) { case OP_ADDI: case OP_ADDIU: + case OP_DADDI: + case OP_DADDIU: if (insn.IType.rs != SP || insn.IType.rt != SP) break; stacksize = -(short)insn.IType.imm; break; case OP_SW: + case OP_SD: if (insn.IType.rs != SP || insn.IType.rt != RA) break; ra_stack_pos = (short)insn.IType.imm; @@ -88,13 +91,13 @@ break; for (i = pc; !ra; i += sizeof (insn)) { - bcopy((void *)i, &insn, sizeof insn); + bcopy((void *)(intptr_t)i, &insn, sizeof insn); switch (insn.IType.op) { case OP_SPECIAL: if((insn.RType.func == OP_JR)) { - if (ra >= (u_register_t)btext) + if (ra >= (u_register_t)(intptr_t)btext) break; if (insn.RType.rs != RA) break; Index: sys/mips/mips/trap.c =================================================================== --- sys/mips/mips/trap.c (revision 209367) +++ sys/mips/mips/trap.c (working copy) @@ -625,6 +625,15 @@ code = locr0->v0; switch (code) { +#if defined(__mips_n32) || defined(__mips_n64) + case SYS___syscall: + /* + * Quads fit in a single register in + * new ABIs. + * + * XXX o64? + */ +#endif case SYS_syscall: /* * Code is first argument, followed by @@ -635,8 +644,16 @@ args[1] = locr0->a2; args[2] = locr0->a3; nsaved = 3; +#if defined(__mips_n32) || defined(__mips_n64) + args[3] = locr0->t4; + args[4] = locr0->t5; + args[5] = locr0->t6; + args[6] = locr0->t7; + nsaved += 4; +#endif break; +#if defined(__mips_o32) case SYS___syscall: /* * Like syscall, but code is a quad, so as @@ -652,6 +669,7 @@ args[1] = locr0->a3; nsaved = 2; break; +#endif default: args[0] = locr0->a0; @@ -659,6 +677,13 @@ args[2] = locr0->a2; args[3] = locr0->a3; nsaved = 4; +#if defined (__mips_n32) || defined(__mips_n64) + args[4] = locr0->t4; + args[5] = locr0->t5; + args[6] = locr0->t6; + args[7] = locr0->t7; + nsaved += 4; +#endif } #ifdef TRAP_DEBUG printf("SYSCALL #%d pid:%u\n", code, p->p_pid); @@ -675,6 +700,15 @@ nargs = callp->sy_narg; if (nargs > nsaved) { +#if defined(__mips_n32) || defined(__mips_n64) + /* + * XXX + * Is this right for new ABIs? I think the 4 there + * should be 8, size there are 8 registers to skip, + * not 4, but I'm not certain. + */ + printf("SYSCALL #%u pid:%u, nargs > nsaved.\n", code, p->p_pid); +#endif i = copyin((caddr_t)(intptr_t)(locr0->sp + 4 * sizeof(register_t)), (caddr_t)&args[nsaved], (u_int)(nargs - nsaved) * sizeof(register_t)); @@ -688,6 +722,18 @@ goto done; } } +#ifdef TRAP_DEBUG + for (i = 0; i < nargs; i++) { + printf("args[%d] = %#jx\n", i, (intmax_t)args[i]); + } +#endif +#ifdef SYSCALL_TRACING + printf("%s(", syscallnames[code]); + for (i = 0; i < nargs; i++) { + printf("%s%#jx", i == 0 ? "" : ", ", (intmax_t)args[i]); + } + printf(")\n"); +#endif #ifdef KTRACE if (KTRPOINT(td, KTR_SYSCALL)) ktrsyscall(code, nargs, args); Index: sys/mips/mips/pm_machdep.c =================================================================== --- sys/mips/mips/pm_machdep.c (revision 209367) +++ sys/mips/mips/pm_machdep.c (working copy) @@ -140,16 +140,16 @@ /* Build the argument list for the signal handler. */ regs->a0 = sig; - regs->a2 = (register_t)&sfp->sf_uc; + regs->a2 = (register_t)(intptr_t)&sfp->sf_uc; if (SIGISMEMBER(psp->ps_siginfo, sig)) { /* Signal handler installed with SA_SIGINFO. */ - regs->a1 = (register_t)&sfp->sf_si; + regs->a1 = (register_t)(intptr_t)&sfp->sf_si; /* sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher; */ /* fill siginfo structure */ sf.sf_si.si_signo = sig; sf.sf_si.si_code = ksi->ksi_code; - sf.sf_si.si_addr = (void*)regs->badvaddr; + sf.sf_si.si_addr = (void*)(intptr_t)regs->badvaddr; } else { /* Old FreeBSD-style arguments. */ regs->a1 = ksi->ksi_code; @@ -172,13 +172,13 @@ sigexit(td, SIGILL); } - regs->pc = (register_t) catcher; - regs->t9 = (register_t) catcher; - regs->sp = (register_t) sfp; + regs->pc = (register_t)(intptr_t)catcher; + regs->t9 = (register_t)(intptr_t)catcher; + regs->sp = (register_t)(intptr_t)sfp; /* * Signal trampoline code is at base of user stack. */ - regs->ra = (register_t) PS_STRINGS - *(p->p_sysent->sv_szsigcode); + regs->ra = (register_t)(intptr_t)PS_STRINGS - *(p->p_sysent->sv_szsigcode); PROC_LOCK(p); mtx_lock(&psp->ps_mtx); } @@ -231,12 +231,12 @@ if (ucp->uc_mcontext.mc_regs[ZERO] != UCONTEXT_MAGIC) { printf("sigreturn: pid %d, ucp %p\n", td->td_proc->p_pid, ucp); printf(" old sp %p ra %p pc %p\n", - (void *)regs->sp, (void *)regs->ra, (void *)regs->pc); + (void *)(intptr_t)regs->sp, (void *)(intptr_t)regs->ra, (void *)(intptr_t)regs->pc); printf(" new sp %p ra %p pc %p z %p\n", - (void *)ucp->uc_mcontext.mc_regs[SP], - (void *)ucp->uc_mcontext.mc_regs[RA], - (void *)ucp->uc_mcontext.mc_regs[PC], - (void *)ucp->uc_mcontext.mc_regs[ZERO]); + (void *)(intptr_t)ucp->uc_mcontext.mc_regs[SP], + (void *)(intptr_t)ucp->uc_mcontext.mc_regs[RA], + (void *)(intptr_t)ucp->uc_mcontext.mc_regs[PC], + (void *)(intptr_t)ucp->uc_mcontext.mc_regs[ZERO]); return EINVAL; } /* #endif */ @@ -483,12 +483,10 @@ td->td_frame->sp = ((register_t) stack) & ~(sizeof(__int64_t) - 1); td->td_frame->pc = imgp->entry_addr & ~3; td->td_frame->t9 = imgp->entry_addr & ~3; /* abicall req */ -#if 0 -// td->td_frame->sr = SR_KSU_USER | SR_EXL | SR_INT_ENAB; -//? td->td_frame->sr |= idle_mask & ALL_INT_MASK; -#else td->td_frame->sr = SR_KSU_USER | SR_EXL | SR_INT_ENAB | (mips_rd_status() & ALL_INT_MASK); +#if defined(__mips_n32) || defined(__mips_n64) + td->td_frame->sr |= SR_PX; #endif #ifdef TARGET_OCTEON td->td_frame->sr |= MIPS_SR_COP_2_BIT | MIPS32_SR_PX | MIPS_SR_UX | [-- Attachment #3 --] Index: sys/conf/ldscript.mips.n32 =================================================================== --- sys/conf/ldscript.mips.n32 (revision 0) +++ sys/conf/ldscript.mips.n32 (revision 0) @@ -0,0 +1,303 @@ +/*- + * Copyright (c) 2001, 2004, 2008, Juniper Networks, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Juniper Networks, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY JUNIPER NETWORKS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL JUNIPER NETWORKS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * JNPR: ldscript.mips,v 1.3 2006/10/11 06:12:04 + * $FreeBSD$ + */ + +OUTPUT_FORMAT("elf32-ntradbigmips", "elf32-ntradbigmips", + "elf32-ntradlittlemips") + +OUTPUT_ARCH(mips) +ENTRY(_start) +SEARCH_DIR(/usr/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; +PROVIDE (_DYNAMIC = 0); +*/ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = KERNLOADADDR + SIZEOF_HEADERS; + .text : + { + *(.trap) + *(.text) + *(.text.*) + *(.stub) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + *(.gnu.linkonce.t.*) + } =0x1000000 + .fini : + { + KEEP (*(.fini)) + } =0x1000000 + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + .rodata : { *(.rodata) *(.rodata.*) *(.gnu.linkonce.r.*) } + .rodata1 : { *(.rodata1) } + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .gnu.version : { *(.gnu.version) } + .gnu.version_d : { *(.gnu.version_d) } + .gnu.version_r : { *(.gnu.version_r) } + .rel.init : { *(.rel.init) } + .rela.init : { *(.rela.init) } + .rel.text : + { + *(.rel.text) + *(.rel.text.*) + *(.rel.gnu.linkonce.t.*) + } + .rela.text : + { + *(.rela.text) + *(.rela.text.*) + *(.rela.gnu.linkonce.t.*) + } + .rel.fini : { *(.rel.fini) } + .rela.fini : { *(.rela.fini) } + .rel.rodata : + { + *(.rel.rodata) + *(.rel.rodata.*) + *(.rel.gnu.linkonce.r.*) + } + .rela.rodata : + { + *(.rela.rodata) + *(.rela.rodata.*) + *(.rela.gnu.linkonce.r.*) + } + .rel.data : + { + *(.rel.data) + *(.rel.data.*) + *(.rel.gnu.linkonce.d.*) + } + .rela.data : + { + *(.rela.data) + *(.rela.data.*) + *(.rela.gnu.linkonce.d.*) + } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.sdata : + { + *(.rel.sdata) + *(.rel.sdata.*) + *(.rel.gnu.linkonce.s.*) + } + .rela.sdata : + { + *(.rela.sdata) + *(.rela.sdata.*) + *(.rela.gnu.linkonce.s.*) + } + .rel.sbss : + { + *(.rel.sbss) + *(.rel.sbss.*) + *(.rel.gnu.linkonce.sb.*) + } + .rela.sbss : + { + *(.rela.sbss) + *(.rela.sbss.*) + *(.rel.gnu.linkonce.sb.*) + } + .rel.sdata2 : + { + *(.rel.sdata2) + *(.rel.sdata2.*) + *(.rel.gnu.linkonce.s2.*) + } + .rela.sdata2 : + { + *(.rela.sdata2) + *(.rela.sdata2.*) + *(.rela.gnu.linkonce.s2.*) + } + .rel.sbss2 : + { + *(.rel.sbss2) + *(.rel.sbss2.*) + *(.rel.gnu.linkonce.sb2.*) + } + .rela.sbss2 : + { + *(.rela.sbss2) + *(.rela.sbss2.*) + *(.rela.gnu.linkonce.sb2.*) + } + .rel.bss : + { + *(.rel.bss) + *(.rel.bss.*) + *(.rel.gnu.linkonce.b.*) + } + .rela.bss : + { + *(.rela.bss) + *(.rela.bss.*) + *(.rela.gnu.linkonce.b.*) + } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : + { + KEEP (*(.init)) + } =0x1000000 + .reginfo : { *(.reginfo) } + .sdata2 : { *(.sdata2) *(.sdata2.*) *(.gnu.linkonce.s2.*) } + .sbss2 : { *(.sbss2) *(.sbss2.*) *(.gnu.linkonce.sb2.*) } + . = ALIGN(0x2000) + (. & (0x2000 - 1)); + .data : + { + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + SORT(CONSTRUCTORS) + } + .data1 : { *(.data1) } + .eh_frame : { KEEP (*(.eh_frame)) } + .gcc_except_table : { *(.gcc_except_table) } + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } + .plt : { *(.plt) } + _gp = ALIGN(16) + 0x7ff0; + .got : { *(.got.plt) *(.got) } + .dynamic : { *(.dynamic) } + /* We want the small data sections together, so single-instruction offsets + can access them all, and initialized data all before uninitialized, so + we can shorten the on-disk segment size. */ + .sdata : + { + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + } + _edata = .; + PROVIDE (edata = .); + __bss_start = .; + .sbss : + { + PROVIDE (__sbss_start = .); + PROVIDE (___sbss_start = .); + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + PROVIDE (__sbss_end = .); + PROVIDE (___sbss_end = .); + } + .bss : + { + *(.dynbss) + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ + . = ALIGN(64 / 8); + } + . = ALIGN(64 / 8); + _end = .; + PROVIDE (end = .); + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info) *(.gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + /* These must appear regardless of . */ +} Index: sys/mips/conf/XLRN32 =================================================================== --- sys/mips/conf/XLRN32 (revision 0) +++ sys/mips/conf/XLRN32 (revision 0) @@ -0,0 +1,163 @@ +#################################RMI_BSD##################################### +# Copyright (c) 2003-2009 RMI Corporation +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# 3. Neither the name of RMI Corporation, nor the names of its contributors, +# may be used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +# SUCH DAMAGE. +#################################RMI_BSD##################################### +# XLR -- Generic kernel configuration file for FreeBSD/mips +# +# For more information on this file, please read the handbook section on +# Kernel Configuration Files: +# +# http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html +# +# The handbook is also available locally in /usr/share/doc/handbook +# if you've installed the doc distribution, otherwise always see the +# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the +# latest information. +# +# An exhaustive list of options and more detailed explanations of the +# device lines is also present in the ../../conf/NOTES and NOTES files. +# If you are in doubt as to the purpose or necessity of a line, check first +# in NOTES. +# +# $FreeBSD: head/sys/mips/conf/XLR 208165 2010-05-16 19:43:48Z rrs $ + +machine mips +cpu CPU_MIPS4KC +ident XLR + +makeoptions MODULES_OVERRIDE="" +makeoptions TARGET_BIG_ENDIAN +# + +include "../rmi/std.xlr" + + +makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols +makeoptions ARCH_FLAGS="-march=mips64 -mabi=n32" +makeoptions LDSCRIPT_NAME=ldscript.mips.n32 + +#profile 2 + +options SCHED_ULE # ULE scheduler +#options VERBOSE_SYSINIT +#options SCHED_4BSD # 4BSD scheduler +options SMP +options PREEMPTION # Enable kernel thread preemption +#options FULL_PREEMPTION # Enable kernel thread preemption +options INET # InterNETworking +options INET6 # IPv6 communications protocols +options FFS # Berkeley Fast Filesystem +#options SOFTUPDATES # Enable FFS soft updates support +options UFS_ACL # Support for access control lists +options UFS_DIRHASH # Improve performance on big directories +options NFSCLIENT +options NFS_ROOT +# +options BOOTP +options BOOTP_NFSROOT +options BOOTP_NFSV3 +options BOOTP_WIRED_TO=rge0 +options BOOTP_COMPAT +options ROOTDEVNAME=\"nfs:10.1.1.8:/usr/extra/nfsroot\" +# +#options MD_ROOT # MD is a potential root device +#options MD_ROOT_SIZE=27000 +#options MD_ROOT_SIZE=5120 +#options ROOTDEVNAME=\"ufs:md0\" +options _KPOSIX_PRIORITY_SCHEDULING # POSIX P1003_1B real-time extensions +options HZ=1000 +options NO_SWAPPING + +#Debugging options +options KTRACE # ktrace(1) support +options DDB +options KDB +options GDB +options ALT_BREAK_TO_DEBUGGER +#options DEADLKRES #Enable the deadlock resolver +options INVARIANTS #Enable calls of extra sanity checking +options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS +#options WITNESS #Enable checks to detect deadlocks and cycles +#options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed +#options KTR # ktr(4) and ktrdump(8) support +#options KTR_COMPILE=(KTR_LOCK|KTR_PROC|KTR_INTR|KTR_CALLOUT|KTR_UMA|KTR_SYSC|KTR_CRITICAL) +#options KTR_ENTRIES=131072 +#options MUTEX_DEBUG +#options MUTEX_PROFILING + +device pci +#device ata +#device atadisk +#options XLR_PERFMON # Enable XLR processor activity monitoring +options BREAK_TO_DEBUGGER +#device genclock +device uart +# Pseudo +device loop +device random +device md +device mem +device pty +device bpf + +# Network +device miibus +device rge +device ether +device re +device msk + +device da +device scbus +#device ohci # OHCI PCI->USB interface +device ehci # EHCI PCI->USB interface (USB 2.0) +device usb # USB Bus (required) +options USB_DEBUG # enable debug msgs +#device udbp # USB Double Bulk Pipe devices +#device ugen # Generic +#device uhid # "Human Interface Devices" +device umass # Disks/Mass storage - Requires scbus and da + +#device cfi + +#i2c +# Not yet +#device ic +#device iic +#device iicbb +#device iicbus +#device xlr_rtc +#device xlr_temperature +#device xlr_eeprom + +#crypto +# Not yet +#device cryptodev +#device crypto +#device rmisec +options ISA_MIPS64 +makeoptions KERNLOADADDR=0x80100000
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