Date: Mon, 2 Jul 2007 18:08:32 -0700 From: Suleiman Souhlal <ssouhlal@FreeBSD.org> To: Attilio Rao <attilio@freebsd.org> Cc: Jeff Roberson <jroberson@chesapeake.net>, current@freebsd.org Subject: Re: New SCHED_SMP diff. Message-ID: <B6C85587-DAFA-4222-89AB-BB9A072E57B6@FreeBSD.org> In-Reply-To: <3bbf2fe10707021518l3d4257d6o3b8838faa6d1ace5@mail.gmail.com> References: <20070701224452.I552@10.0.0.1> <20070701224741.M552@10.0.0.1> <3bbf2fe10707021518l3d4257d6o3b8838faa6d1ace5@mail.gmail.com>
next in thread | previous in thread | raw e-mail | index | archive | help
On Jul 2, 2007, at 3:18 PM, Attilio Rao wrote: > 2007/7/2, Jeff Roberson <jroberson@chesapeake.net>: >> I forgot: >> >> http://people.freebsd.org/~jeff/schedsmp.diff >> >> --- amd64/amd64/cpu_switch.S 6 Jun 2007 07:35:07 -0000 1.158 >> +++ amd64/amd64/cpu_switch.S 2 Jul 2007 05:43:31 -0000 >> @@ -148,13 +148,7 @@ >> movq %cr3,%rax >> cmpq %rcx,%rax /* Same address space? */ >> jne swinact >> - movq %rdx, TD_LOCK(%rdi) /* Release the old thread */ >> - /* Wait for the new thread to become unblocked */ >> - movq $blocked_lock, %rdx >> -1: >> - movq TD_LOCK(%rsi),%rcx >> - cmpq %rcx, %rdx >> - je 1b >> + xchgq %rdx, TD_LOCK(%rdi) /* Release the old thread */ > > I don't think here you need an atomic instruction, a memory barrier > throug sfence is good enough in order to make thread migration > consistent. SFENCE is not needed. Stores are already strongly ordered wrt other stores on x86 (unless you use write-combining memory or non-temporal stores). The main advantage of using an atomic operation when unlocking is that it should make the store visible to other CPUs faster (so they don't spin as long), although I think you'll have a hard time noticing a difference in a macrobenchmark. -- Suleiman
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?B6C85587-DAFA-4222-89AB-BB9A072E57B6>