Date: Tue, 4 Oct 2011 23:17:54 +0530 From: "Jayachandran C." <jchandra@freebsd.org> To: Andrew Duane <aduane@juniper.net> Cc: Kostik Belousov <kostikbel@gmail.com>, Alexander Motin <mav@freebsd.org>, "freebsd-mips@freebsd.org" <freebsd-mips@freebsd.org> Subject: Re: svn commit: r225892 - head/sys/mips/mips Message-ID: <CA%2B7sy7AncTdRDN88DaiPsBDc=PQ3N6UR9VAb7chOOp7XDXS=Sw@mail.gmail.com> In-Reply-To: <AC6674AB7BC78549BB231821ABF7A9AEB80CB1FE93@EMBX01-WF.jnpr.net> References: <kor1ebmmdclae4u7bstwrc2c.1317741744919@email.android.com> <AC6674AB7BC78549BB231821ABF7A9AEB80CB1FE93@EMBX01-WF.jnpr.net>
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On Tue, Oct 4, 2011 at 9:34 PM, Andrew Duane <aduane@juniper.net> wrote: > The MIPS manual volume 3 says there is a 3 cycle "typical" wait between a= n MTC0 that messes with Status[IE] and an interrupted instruction. That haz= ard doesn't seem to apply here, to any of the cases we have. > > I do have a question: in StartWaitSkip, the value of Status[IE] is being = toggled, not cleared. Is that correct? Do we always guarantee that it will = be set on entry here? Interrupts have to be enabled in cpu_idle(), there is an assert in the beginning of cpu_idle which checks this. > I had also made a comment about the "PTR_ADDU k1, 16 =A0 =A0# skip over w= ait" in MipsKernIntr; I think it would be safer (and clearer) to do "PTR_LA= =A0 =A0 =A0 =A0k1, EndWaitSkip" instead. Loading an immediate address takes more instructions (esp in 64 bit) adding 16 is just one instruction. I should really add an KASSERT somewhere to make sure that EndWaitSkip - StartWaitSkip is 16... JC.
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