Date: Sat, 22 Dec 2018 22:46:49 +0530 From: nilakshan kunananthaseelan <nilakjhc@gmail.com> To: freebsd-riscv@freebsd.org Subject: FreeBSD for RISC-V 32 Message-ID: <CA%2Bpg%2B_J5=hyn2VrWeJbYx-zHs3V%2BU3cD%2B7CrWyDygJQMr4SsnA@mail.gmail.com>
next in thread | raw e-mail | index | archive | help
Hi all, We are developing a 32 bit processor based on RISC-V.So far we have developed M and A extension and we have developed TLB for data and instruction.In the CSR we have included the machine and supervisor mode(tested with RISCV benchmark hex file).I have some issues regarding porting a kernel for RISCV? 1.If CSR testing is OK with RISCV benchmark hex file may I plug this into the core system.If not is there any particular method to identify the flow of CSR? 2.Will freeBSD supports 32 bit machine?If so,what additional things I have to do to port freeBSD for my processor? What are the changes to be done for the steps given her https://wiki.freebsd.org/riscv? thanks in advance -Nilakshan
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?CA%2Bpg%2B_J5=hyn2VrWeJbYx-zHs3V%2BU3cD%2B7CrWyDygJQMr4SsnA>