Date: Sun, 4 Nov 2012 15:54:42 -0800 From: Juli Mallett <juli@clockworksquid.com> To: "freebsd-mips@FreeBSD.org" <freebsd-mips@freebsd.org> Subject: CACHE_LINE_SIZE macro. Message-ID: <CACVs6=_BrwJ19CPj7OqKvV8boHfujVWqn96u3VPUmZ040JpAeQ@mail.gmail.com>
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Fellow FreeBSD/MIPSists, CACHE_LINE_SIZE is being used increasingly-much in ways which may have ABI implications, etc. It is currentyl 2^6, whereas at least the Cavium Octeon has cache lines that are actually 2^7 bytes in size. It would be nice to expose the correct value to reduce false line sharing, etc., but making it dependent on the CPU type raises ABI issues, as well as questions about how to reliably get the right value to userland. It seems to me that increasing it to 2^7 is the most viable approach, but I can imagine there might be some concerns about that, so I wanted to run it past this list first. Questions, comments, concerns? Are there MIPS CPUs with 2^8-byte or larger cache lines that we support or will support or which are likely coming over the horizon? Thanks, Juli.
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