Date: Fri, 5 Apr 2013 10:57:06 -0400 From: Patrick Kelsey <kelsey@ieee.org> To: Dmytro <dioptimizer@gmail.com> Cc: freebsd-mips@freebsd.org Subject: Re: [PATCH] MMC/SD SPI-mode driver Message-ID: <CAD44qMURrssyXUz-%2Btd226chPA_MbKJ29ZApozbT2cEYbQwSqw@mail.gmail.com> In-Reply-To: <CAK1zEjuVZU4A59q5GxLcKTnFF9mcrbVmJ=w268uSJ=3sxVf1PA@mail.gmail.com> References: <CAK1zEjs=hC%2BpAYBgGq4t7%2BA_JPLaH6rhvEjD%2B1RNk1Ziu8E-4g@mail.gmail.com> <CAD44qMWpz-sjNKwRH6K=xicFXYutfk7R%2BN%2B%2Bo7cbgTg7rcQbkA@mail.gmail.com> <CAK1zEjuVZU4A59q5GxLcKTnFF9mcrbVmJ=w268uSJ=3sxVf1PA@mail.gmail.com>
next in thread | previous in thread | raw e-mail | index | archive | help
On Thu, Apr 4, 2013 at 11:11 PM, Dmytro <dioptimizer@gmail.com> wrote: > Thank you Patrick for the detailed answers. > Given the platform processors Atheros, it is safe to say that all line > ath79 (AR71XX/AR724X/AR913X SoCs) - SPI generic and has not changed > even in the new generations of this CPUs. > Working in OpenWRT, I can say that reading speed/CPU load is about the > same as yours - slow. > But I did not quite understand how to implemented the function of fast > reading for NOR flash memory in driver (m25p80.c). > Reading speed of NOR flash-memory about 3 MB/Without a full load CPU. > I understand that it is sent to a specific command/register for a fast > read is also SPI uses the buffer of NOR chip . > However, at what level SPI controller is programmed for increasing > speed - is not clear. > http://dioptimizer.narod.ru/files/spi-ath79.c > My understanding is that in the AR71xx (and possibly other related Atheros SoCs), the boot flash can be read through memory mapped access to a region starting at the reset address, as this is how booting from a serial flash is accomplished. In that scenario, the SPI controller will be translating each read access into an SPI bus transaction that will produce the desired data from the flash. Since the hardware is performing the SPI signalling, you wouldn't have the CPU overhead of bitbanging each SPI bit out. Performance would still be limited by the value set in the SPI clock divider register (which controls the bit times on the wire) and the speed of the clock that runs the SPI unit itself. -Patrick
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?CAD44qMURrssyXUz-%2Btd226chPA_MbKJ29ZApozbT2cEYbQwSqw>