Date: Sun, 11 Mar 2012 11:19:03 -0400 From: Patrick Kelsey <kelsey@ieee.org> To: Adrian Chadd <adrian@freebsd.org> Cc: freebsd-mips@freebsd.org Subject: Re: [PATCH] MikroTik RB450G support Message-ID: <CAD44qMWkWB6eqe%2BXyfFq9Tam=OLPowiMEgri_8BYw9AbPbdK6Q@mail.gmail.com> In-Reply-To: <CAJ-VmomZiutERg4YcTDUCAOC9Wwx5Gsdei4E-iSvszAw6H81SQ@mail.gmail.com> References: <CAD44qMV=PEv3DFU7z1S=UhOYO3YMi7zqg7rsjn1zByTpN7ZxgA@mail.gmail.com> <CAJ-VmomZiutERg4YcTDUCAOC9Wwx5Gsdei4E-iSvszAw6H81SQ@mail.gmail.com>
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[-- Attachment #1 --]
On Sat, Mar 10, 2012 at 10:44 PM, Adrian Chadd <adrian@freebsd.org> wrote:
> Thanks for this!
Thanks for taking a look!
> The arge patch for board info should be something chip specific,
> rather than always compiled in.
>
> The board model thing should be an environment variable, rather than
> hard-coded in the driver. What's it needed for, anyway? Are the MAC
> addresses reversed?
On the RB450G, the typical config seems to be to have arge1 connected
to the lowest numbered front panel port, with the base MAC address
assigned. In the updated patch (attached), I did away with the board
model logic and replaced it with a mac_offset hint, which is a generic
solution that is also more concise and flexible.
I also cleaned up the patch to ar71xx_machdep.c, which was needlessly
putting the board_model in a global when it was already available in
the environment via the existing HEAD code. The only change remaining
then for the RB450 is to extract the mem size from argv.
> The MII speed thing is good, I've been wondering about adding more MII
> config stuff to the ar71xx code. But we'll have to ensure it's set
> correctly for the AR91xx and AR724x code.
I currently have no knowledge of the AR91xx and AR724x requirements.
As far as I can tell, and I'm not authoritative on this by any means,
setting the MII speed on AR71xx is only relevant when operating in
MII/RMII mode. The RB450G runs in RGMII mode, and empirically doesn't
seem to be affected by setting the MII speed to any value, so I'd have
no objection if this part of the patch is put off until questions can
be resolved. Perhaps this should be broken out into a separate patch.
-Patrick
[-- Attachment #2 --]
Index: sys/mips/conf/RB450.hints
===================================================================
--- sys/mips/conf/RB450.hints (revision 0)
+++ sys/mips/conf/RB450.hints (revision 0)
@@ -0,0 +1,72 @@
+#
+# $FreeBSD$
+#
+hint.apb.0.at="nexus0"
+hint.apb.0.irq=4
+
+# uart0
+hint.uart.0.at="apb0"
+# see atheros/uart_cpu_ar71xx.c why +3
+hint.uart.0.maddr=0x18020003
+hint.uart.0.msize=0x18
+hint.uart.0.irq=3
+
+#ohci
+#hint.ohci.0.at="apb0"
+#hint.ohci.0.maddr=0x1c000000
+#hint.ohci.0.msize=0x01000000
+#hint.ohci.0.irq=6
+
+#ehci
+#hint.ehci.0.at="nexus0"
+#hint.ehci.0.maddr=0x1b000000
+#hint.ehci.0.msize=0x01000000
+#hint.ehci.0.irq=1
+
+# pci
+#hint.pcib.0.at="nexus0"
+#hint.pcib.0.irq=0
+
+hint.arge.0.at="nexus0"
+hint.arge.0.maddr=0x19000000
+hint.arge.0.msize=0x1000
+hint.arge.0.irq=2
+# PHY0, PHY1, PHY2, PHY3
+hint.arge.0.phymask=0x0f
+hint.arge.0.mac_offset=1
+
+hint.arge.1.at="nexus0"
+hint.arge.1.maddr=0x1A000000
+hint.arge.1.msize=0x1000
+hint.arge.1.irq=3
+# PHY4
+hint.arge.1.phymask=0x10
+hint.arge.1.mac_offset=0
+
+# SPI controller
+hint.spi.0.at="nexus0"
+hint.spi.0.maddr=0x1f000000
+hint.spi.0.msize=0x10
+
+# SPI microSD slot
+hint.mmcspi.0.at="spibus0"
+hint.mmcspi.0.cs=2
+
+# Watchdog
+hint.ar71xx_wdog.0.at="nexus0"
+
+# GPIO
+hint.gpio.0.at="apb0"
+hint.gpio.0.maddr=0x18040000
+hint.gpio.0.msize=0x1000
+hint.gpio.0.irq=2
+
+# User led
+hint.gpioled.0.at="gpiobus0"
+hint.gpioled.0.name="user"
+# pin 4
+hint.gpioled.0.pins=0x0010
+
+# hwpmc device
+hint.ar71xx_pmc.0.at="apb0"
+hint.ar71xx_pmc.0.irq=5
Index: sys/mips/conf/RB4XX
===================================================================
--- sys/mips/conf/RB4XX (revision 0)
+++ sys/mips/conf/RB4XX (revision 0)
@@ -0,0 +1,132 @@
+#
+# $FreeBSD$
+#
+
+ident RB4XX
+makeoptions TARGET_BIG_ENDIAN
+makeoptions KERNLOADADDR=0x80050000
+options HZ=1000
+options HWPMC_HOOKS
+
+hints "RB450.hints"
+
+include "../atheros/std.ar71xx"
+
+#makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols
+makeoptions MODULES_OVERRIDE=""
+
+#options DDB
+#options KDB
+
+options SCHED_4BSD #4BSD scheduler
+options INET #InterNETworking
+options NFSCL #Network Filesystem Client
+options NFSCLIENT #Network Filesystem Client
+options NFS_ROOT #NFS usable as /, requires NFSCLIENT
+options PSEUDOFS #Pseudo-filesystem framework
+options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions
+
+# options NFS_LEGACYRPC
+# Debugging for use in -current
+# options INVARIANTS
+# options INVARIANT_SUPPORT
+# options WITNESS
+# options WITNESS_SKIPSPIN
+# options DEBUG_REDZONE
+# options DEBUG_MEMGUARD
+options FFS #Berkeley Fast Filesystem
+options SOFTUPDATES #Enable FFS soft updates support
+options UFS_ACL #Support for access control lists
+options UFS_DIRHASH #Improve performance on big directories
+
+options MSDOSFS
+
+options BOOTP
+options BOOTP_NFSROOT
+options BOOTP_NFSV3
+options BOOTP_WIRED_TO=arge1
+options BOOTP_COMPAT
+options ROOTDEVNAME=\"nfs:freebsd82dev64:/nfsroot/rb4xx\"
+
+device pci
+device ar71xx_pci
+
+# 802.11 framework
+# options IEEE80211_DEBUG
+# options IEEE80211_ALQ
+# options IEEE80211_SUPPORT_MESH
+# This option is currently broken for if_ath_tx.
+# options IEEE80211_SUPPORT_TDMA
+# options IEEE80211_AMPDU_AGE
+# device wlan # 802.11 support
+# device wlan_wep # 802.11 WEP support
+# device wlan_ccmp # 802.11 CCMP support
+# device wlan_tkip # 802.11 TKIP support
+# device wlan_xauth # 802.11 hostap support
+
+# Atheros wireless NICs
+# device ath # Atheros interface support
+# device ath_pci # Atheros PCI/Cardbus bus
+# options ATH_DEBUG
+# options ATH_DIAGAPI
+# options ATH_ENABLE_11N
+# options AH_DEBUG
+# options AH_DEBUG_ALQ
+# options ALQ
+# device ath_hal
+# option AH_SUPPORT_AR5416
+# device ath_rate_sample
+# option AH_RXCFG_SDMAMW_4BYTES
+# option AH_AR5416_INTERRUPT_MITIGATION
+# There's no DFS radar detection support yet so this won't actually
+# detect radars. It however does enable the rest of the channel change
+# machinery so DFS can be debugged.
+# option ATH_ENABLE_DFS
+
+device mii
+device arge
+
+# device usb
+# options USB_EHCI_BIG_ENDIAN_DESC # handle big-endian byte order
+# options USB_DEBUG
+# device ehci
+
+# device scbus
+# device umass
+# device da
+
+device spibus
+device ar71xx_spi
+device mmc
+device mmcsd
+device mmcspi
+device ar71xx_wdog
+
+device uart
+
+device loop
+device ether
+device md
+device bpf
+device random
+device if_bridge
+# device gif # ip[46] in ip[46] tunneling protocol
+# device gre # generic encapsulation - only for IPv4 in IPv4 though atm
+
+# options ARGE_DEBUG # Enable if_arge debugging for now
+
+device gpio
+device gpioled
+
+#options RB_GPIO_PINS
+#options FIX_RB_MAC_ADDRESS
+
+options DUMMYNET
+options LIBALIAS
+options IPDIVERT
+options IPSTEALTH
+options IPFIREWALL
+options IPFIREWALL_NAT
+options IPFIREWALL_FORWARD
+options IPFIREWALL_VERBOSE
+options IPFIREWALL_DEFAULT_TO_ACCEPT
Index: sys/mips/atheros/ar71xx_machdep.c
===================================================================
--- sys/mips/atheros/ar71xx_machdep.c (revision 232725)
+++ sys/mips/atheros/ar71xx_machdep.c (working copy)
@@ -169,7 +169,7 @@
__register_t a2 __unused, __register_t a3 __unused)
{
uint64_t platform_counter_freq;
- int argc = 0, i;
+ int argc = 0, i, board_mem;
char **argv = NULL, **envp = NULL;
vm_offset_t kernend;
@@ -207,6 +207,16 @@
}
}
+ /* RouterBOOT passes the mem size in argv */
+ if ((0 == realmem) && MIPS_IS_VALID_PTR(argv)) {
+ for (i = 0; i < argc; i++) {
+ if (strncmp(argv[i], "mem=", 4) == 0) {
+ if (sscanf(argv[i] + 4, "%dM", &board_mem) == 1)
+ realmem = btoc(board_mem * 1024 * 1024);
+ }
+ }
+ }
+
/*
* Just wild guess. RedBoot let us down and didn't reported
* memory size
Index: sys/mips/atheros/if_arge.c
===================================================================
--- sys/mips/atheros/if_arge.c (revision 232725)
+++ sys/mips/atheros/if_arge.c (working copy)
@@ -242,7 +243,7 @@
int error = 0, rid, phymask;
uint32_t reg, rnd;
int is_base_mac_empty, i, phys_total;
- uint32_t hint;
+ uint32_t hint, mac_offset;
long eeprom_mac_addr = 0;
sc = device_get_softc(dev);
@@ -394,8 +395,12 @@
eaddr[5] = (rnd >> 8) & 0xff;
}
- if (sc->arge_mac_unit != 0)
- eaddr[5] += sc->arge_mac_unit;
+ if (resource_int_value(device_get_name(dev), device_get_unit(dev),
+ "mac_offset", &mac_offset) != 0) {
+ eaddr[5] += mac_offset;
+ } else {
+ eaddr[5] += sc->arge_mac_unit;
+ }
if (arge_dma_alloc(sc) != 0) {
error = ENXIO;
Index: sys/mips/atheros/ar71xx_chip.c
===================================================================
--- sys/mips/atheros/ar71xx_chip.c (revision 232725)
+++ sys/mips/atheros/ar71xx_chip.c (working copy)
@@ -136,21 +136,35 @@
return ((reg & mask) == mask);
}
+static __inline void
+ar71xx_chip_set_mii_speed(uint32_t reg, uint32_t ctrl)
+{
+ uint32_t val;
+
+ val = ATH_READ_REG(reg);
+ val &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT);
+ val |= (ctrl & MII_CTRL_SPEED_MASK) << MII_CTRL_SPEED_SHIFT;
+ ATH_WRITE_REG(reg, val);
+}
+
/* Speed is either 10, 100 or 1000 */
static void
ar71xx_chip_set_pll_ge(int unit, int speed)
{
- uint32_t pll;
+ uint32_t ctrl, pll;
switch (speed) {
case 10:
pll = PLL_ETH_INT_CLK_10;
+ ctrl = MII_CTRL_SPEED_10;
break;
case 100:
pll = PLL_ETH_INT_CLK_100;
+ ctrl = MII_CTRL_SPEED_100;
break;
case 1000:
pll = PLL_ETH_INT_CLK_1000;
+ ctrl = MII_CTRL_SPEED_1000;
break;
default:
printf("%s%d: invalid speed %d\n",
@@ -162,11 +176,13 @@
ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG,
AR71XX_PLL_ETH_INT0_CLK, pll,
AR71XX_PLL_ETH0_SHIFT);
+ ar71xx_chip_set_mii_speed(AR71XX_MII0_CTRL, ctrl);
break;
case 1:
ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG,
AR71XX_PLL_ETH_INT1_CLK, pll,
AR71XX_PLL_ETH1_SHIFT);
+ ar71xx_chip_set_mii_speed(AR71XX_MII1_CTRL, ctrl);
break;
default:
printf("%s: invalid PLL set for arge unit: %d\n",
Index: sys/mips/atheros/ar71xxreg.h
===================================================================
--- sys/mips/atheros/ar71xxreg.h (revision 232725)
+++ sys/mips/atheros/ar71xxreg.h (working copy)
@@ -270,6 +270,13 @@
/*
* GigE adapters region
*/
+#define AR71XX_MII0_CTRL 0x18070000
+#define AR71XX_MII1_CTRL 0x18070004
+#define MII_CTRL_SPEED_SHIFT 4
+#define MII_CTRL_SPEED_MASK 3
+#define MII_CTRL_SPEED_10 0
+#define MII_CTRL_SPEED_100 1
+#define MII_CTRL_SPEED_1000 2
#define AR71XX_MAC0_BASE 0x19000000
#define AR71XX_MAC1_BASE 0x1A000000
/*
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