Date: Wed, 28 Jan 2015 15:16:48 +0100 From: Svatopluk Kraus <onwahe@gmail.com> To: freebsd-arm@freebsd.org Subject: Re: interrupt framework Message-ID: <CAFHCsPVhRnRXhLF6S-%2BDL5mM22X0CkMmKOkkuo0DOMShkEM=fQ@mail.gmail.com> In-Reply-To: <CAFHCsPX5kG_v-F-cjpyMQsT_b386eok=mqWW0%2BEUb_4-_1Otnw@mail.gmail.com> References: <CAFHCsPX5kG_v-F-cjpyMQsT_b386eok=mqWW0%2BEUb_4-_1Otnw@mail.gmail.com>
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--001a11c13d0eaf1b20050db7058a Content-Type: text/plain; charset=UTF-8 New ARM interrupt framework is implemented fully now. At this moment, only GIC interrupt controller is working with this framework and it was tested on pandaboard. I'm going to change all other ARM interrupt controllers in source tree, however, I will else be able to test only the ones related to BBB and Raspberry Pi. The testing was done only according to old framework at this moment. The new features like fast interrupt handling, cascaded controllers, explicit interrupt binding and describing were not tested. However, interrupts are now shuffled among all running CPUs by round-robin method according to x86 interrupt framework. Nevertheless, it is just a proof of concept. The way on which CPU(s) an interrupt will be served should be changed as on capable controllers the not bound interrupt could be served on all running CPUs in controller'c CPU cluster. The decision should be always taken by controller (with help of framework if needed). Thus there is still some work on the framework, but I do not suppose any drastic changes. Therefore it is not cleaned up now. It includes changes done in other files too. --------------------------------------- Now, a few words about new framework which have not been said yet. It lays between system and controllers. Communication between system and framework is done by an interrupt number which is opaque to controllers and more like resource handle. AFAIK there are five bus methods: BUS_CONFIG_INTR, BUS_SETUP_INTR, BUS_BIND_INTR, BUS_DESCRIBE_INTR BUS_TEARDOWN_INTR. The order in which I wrote them is much the order in which should be called by a consumer. However, the simplest consumer calls BUS_SETUP_INTR only. New framework is more strict than man pages are in that an interrupt configuration is not permited on active (enabled) interrupt. In other words, BUS_CONFIG_INTR must be called before BUS_SETUP_INTR. BUS_BIND_INTR and BUS_DESCRIBE_INTR are connected to specific handler (MI interrupt framework) so they must be called after BUS_SETUP_INTR. BUS_BIND_INTR binds interrupt's ithread if exists too and BUS_DESCRIBE_INTR describes associated handler. Of course, the order of these two methods can be switched. Communication between framework and a controller is done by an interrupt source (ISRC) which is now made public. It makes an access simpler for controllers, but if there will be many controllers (on more arch possibly), it makes framework modifications harder. So this is still opened question: privite or public? However, for now it's not problem to switch from one way to another. There are six main pic methods: PIC_REGISTER, PIC_ENABLE_INTR, PIC_ENABLE_SOURCE, PIC_DISABLE_SOURCE, PIC_DISABLE_INTR, PIC_UNREGISTER, three suplementary methods: PIC_POST_FILTER, PIC_PRE_ITHREAD, PIC_POST_ITHREAD, and three SMP methods: PIC_BIND, PIC_IPI_SEND, PIC_INIT_SECONDARY. As was said before, an ISRC is created by some mapping function which provides description of the source. This can happen before ISRC's controller is presented in system. So the creation of ISRC is independent on related controller. Provided description must be well known for that controller while it's opaque for framework except one thing. Each mapping fuction must provide an opaque key to ISRC which identificates a controller. Likewise, each controller must register itself to framework with its opaque key. There are two mapping function in the framework now: u_int arm_namespace_map_irq(device_t dev, uint16_t type, uint16_t num); u_int arm_fdt_map_irq(phandle_t node, pcell_t *cells, u_int ncells); Thus ISRC is not connected to related controller at the beginning and must be registered (mapped) to it later. It's done by PIC_REGISTER, but before that a related controller (if not known already) must be found according to saved key. Then in PIC_REGISTER, a controller should evaluate provided ISRC desription and if recognized, do any allocation of related data and save ISRC inside itself for interrupt managing reason. When ISRC is going to be enabled, PIC_ENABLE_INTR and PIC_ENABLE_SOURCE are called. In PIC_ENABLE_INTR, a controller is supposed to prepare everything for real enabling of related interrupt. It means doing configuration, binding, whatever is needed. PIC_ENABLE_SOURCE should be simple unmasking of related interrupt and it's called repeatedly during interrupt dispaching. Likewise PIC_DISABLE_SOURCE should be simple masking of related interrupt, PIC_DISABLE_INTR should clean up, and PIC_UNREGISTER should clear any evidence about. While PIC_REGISTER and PIC_UNREGISTER are called without framework locking and it's controller's resposibility to ensure atomicity of registration process, the other four methods are called with framework locking. It has simple reason as a controller is supposed to do all hard work for an ISRC (allocation) in PIC_REGISTER and PIC_UNREGISTER. The suplementary methods are presented due to using of MI interrupt framework and should be tailored exactly for its needs. The using of SMP methods are obvious. The IPIs are setup on a controller by same PIC_REGISTER method as standard interrupts with use of namespace mapping functions. The cpu argument passed to PIC_BIND is an integer (not cpuset_t) as MI interface binding methods works only with single cpu. --------------------------------------- Finally a few words about removable controllers. It should be no problem as we are in kernel. At least as long as everybody will act correctly. Suprisingly, it will be only problem of interrupt counting because of the way how sysctl and DDB work with it. However, for now, controllers are not removable and once registered ISRC is never unregistered (which is safe as an ISRC should be described always same). Nevertheless, I have pretty ideas for how to make controllers removable. --------------------------------------- The attached diff is made against today's 277826 revision. New framework must be anabled by option ARM_INTRNG in board's configuration file. And debug framework's prints are enabled now. Tomorow I'm leaving the town and will be back on next Thursday, so sorry for any late reply if will be needed in that time. Svata On Thu, Jan 15, 2015 at 2:51 PM, Svatopluk Kraus <onwahe@gmail.com> wrote: > Hi community, > > I and Michal Meloun have done some work on ARM interrupt framework and > this is the result. > > We've started with intrng project with Ian's WIP changes, have looked > at Andrew's ARM64 git repository, and this is how we think an > interrupt framework should look like. We've implemented it with > removable interrupt controllers in mind (PCI world). It's not finished > from this point of view, however some functions are more complex > because of it. > > It's tested on pandaboard and only GIC is implemented now. There is no > problem to implement it to other controllers. We are open to questions > and can finish our work considering any comments. Whoever is waiting > for ARM interrupt framework as we were, you are welcome to test it. > Whoever is welcome. The patches are done against FreeBSD-11-current > revision 277210. There are two new files. > > ARM_INTRNG option must be added to board configuration file for new framework. > > There are still some things not implemented and some things which > should be discussed like PPI support. For example, how to enable PPI > interrupt on other CPUs when they are already running? > > We keep in mind that an interrupt framework should be helpfull but > general enough to not dictate interrupt controlles too much. Thus we > try to keep some things as much separated as possible. Each interrupt > is represented by an interrupt source (ISRC) in the framework. An ISRC > is described by an interrupt number which is much more an unique > resource handle - totally independent on internal representation of > interrupts in any interrupt controller. > > An interrupt is described by cells in FDT world. The cells can be > decoded only by associated interrupt controller and as such, they are > transparent for interrupt framework. The framework provides > arm_fdt_map_irq() function which maps this transparent cells to an > interrupt number. It creates an ISRC, saves cells on it, and once when > associated interrupt controller is registered, it provides the ISRC > with cells into the controller. > > It's a controller responsibility to save an ISRC associated with > cells. An ISRC is transparent for any controller. However, an > controller can set/get its data to/from an ISRC. Further, an > controller should set a name to an ISRC according to internal > representation of associated interrupt. > > An controller interrupt dispatch function can call framework only if > it has associated ISRC to received interrupt. > > For legacy reason, there is arm_namespace_map_irq() function. An > interrupt is described by namespace type and a number from the > namespace. It's intented for use with no FDT drivers. Now, it's used > for mapping an IPI on a controller. > > We think that it's better to call chained controllers (with filter > only) without MI interrupt framework overhead, so we implemented > shortcut. It could be utilized by INTR_SOLO flag during > bus_setup_intr(). > > Only an interrupt controller can really know its position in interrupt > controller's tree. So root controller must claim itself as a root. In > FDT world, according to ePAPR approved version 1.1 from 08 April 2011, > page 30: > > "The root of the interrupt tree is determined when traversal of the > interrupt tree reaches an interrupt controller node without an > interrupts property and thus no explicit interrupt parent." > > Thus there are no need for any non-standard things in DTS files. > > Svata --001a11c13d0eaf1b20050db7058a Content-Type: text/plain; charset=US-ASCII; name="intrng_onwahe3.diff" Content-Disposition: attachment; filename="intrng_onwahe3.diff" Content-Transfer-Encoding: base64 X-Attachment-Id: f_i5gsl5nf5 SW5kZXg6IHN5cy9hcm0vYXJtL2dpYy5jCj09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09 PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT0KLS0tIHN5cy9hcm0vYXJtL2dpYy5j CShyZXZpc2lvbiAyNzc4MjYpCisrKyBzeXMvYXJtL2FybS9naWMuYwkod29ya2luZyBjb3B5KQpA QCAtMzQsNiArMzQsOCBAQAogI2luY2x1ZGUgPHN5cy9jZGVmcy5oPgogX19GQlNESUQoIiRGcmVl QlNEJCIpOwogCisjaW5jbHVkZSAib3B0X3BsYXRmb3JtLmgiCisKICNpbmNsdWRlIDxzeXMvcGFy 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