Date: Wed, 29 Apr 2015 14:59:02 -0500 From: Jason Harmening <jason.harmening@gmail.com> To: Konstantin Belousov <kostikbel@gmail.com> Cc: Svatopluk Kraus <onwahe@gmail.com>, John Baldwin <jhb@freebsd.org>, Adrian Chadd <adrian@freebsd.org>, Warner Losh <imp@bsdimp.com>, freebsd-arch <freebsd-arch@freebsd.org> Subject: Re: bus_dmamap_sync() for bounced client buffers from user address space Message-ID: <CAM=8qak0qRw5MsSG4e1Zqxo_x9VFGQ2rQpjUBFX_UA6P9_-2cA@mail.gmail.com> In-Reply-To: <20150429193337.GQ2390@kib.kiev.ua> References: <38574E63-2D74-4ECB-8D68-09AC76DFB30C@bsdimp.com> <CAJ-VmomqGkEFVauya%2BrmPGcD_-=Z-mmg1RSDf1D2bT_DfwPBGA@mail.gmail.com> <1761247.Bq816CMB8v@ralph.baldwin.cx> <CAFHCsPX9rgmCAPABct84a000NuBPQm5sprOAQr9BTT6Ev6KZcQ@mail.gmail.com> <20150429132017.GM2390@kib.kiev.ua> <CAFHCsPWjEFBF%2B-7SR7EJ3UHP6oAAa9xjbu0CbRaQvd_-6gKuAQ@mail.gmail.com> <20150429165432.GN2390@kib.kiev.ua> <CAM=8qakzkKX8TZNYE33H=JqL_r5z%2BAU9fyp5%2B7Z0mixmF5t63w@mail.gmail.com> <20150429185019.GO2390@kib.kiev.ua> <CAM=8qanPHbCwUeu0-zi-ccY4WprHaOGzCm44PwNSgb==nwgGGw@mail.gmail.com> <20150429193337.GQ2390@kib.kiev.ua>
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> > See the paragraph in my mail before the one you answered. > I am asking about the bcopy()/physcopyout() lines in diff, not about > the if () conditions change. The later is definitely fine. > Oh, yes, sorry. There were a couple of whitespace changes there, but nothing of consequence. > Even without SMP, VIPT cache cannot hold two mappings of the same page. > As I understand, sometimes it is more involved, eg if mappings have > correct color (eg. on ultrasparcs), then cache can deal with aliasing. > Otherwise pmap has to map the page uncached for all mappings. > Yes, you are right. Regardless of whatever logic the cache uses (or doesn't use), FreeBSD's page-coloring scheme should prevent that. > > I do not see what would make this case special for SMP after that. > Cache invalidation would be either not needed, or coherency domain > propagation of the virtual address does the right thing. > Since VIPT cache operations require a virtual address, I'm wondering about the case where different processes are running on different cores, and the same UVA corresponds to a completely different physical page for each of those processes. If the d-cache for each core contains that UVA, then what does it mean when one core issues a flush/invalidate instruction for that UVA? Admittedly, there's a lot I don't know about how that's supposed to work in the arm/mips SMP world. For all I know, the SMP targets could be fully-snooped and we don't need to worry about cache maintenance at all.
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