Date: Wed, 2 Apr 2008 17:23:51 -0700 From: Marcel Moolenaar <xcllnt@mac.com> To: Nathan Whitehorn <nathanw@uchicago.edu> Cc: freebsd-ppc@freebsd.org Subject: Re: BMAC Ethernet Driver Message-ID: <CB59240D-E385-4D4C-9372-E9D418502F61@mac.com> In-Reply-To: <47F422A0.9080907@uchicago.edu> References: <47E06B23.7060400@uchicago.edu> <20080325023040.ab0daa19.stas@FreeBSD.org> <47E8527B.2050002@uchicago.edu> <47F39EF4.8040800@uchicago.edu> <C83E8810-B68B-49B5-A7F4-8B72A4FFFFDA@mac.com> <47F3D2BC.7060001@uchicago.edu> <47F422A0.9080907@uchicago.edu>
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On Apr 2, 2008, at 5:19 PM, Nathan Whitehorn wrote: >>> From what you say it seems that the driver is commitable at >>> this time. I can't test it, but I can definitely commit. >>> Just let me know... >> I would like some tests with one of the other two revisions of the >> chip, of course, but any fixes should be minor. The real concern, >> on my part, for committing it is whether the macio IRQ patch breaks >> anything. If you have both an interrupts property and an >> AAPL,interrupts in OF, with multiple interrupts listed, it will >> cause all of the AAPL,interrupts IRQ resources to be renumbered. >> >> At the moment, we only support two devices (SCC and macio ATA) >> hanging off macio, so the set of things to be checked is limited. I >> know that the ATA code still works, but I suspect it might break >> the scc UART support, since it has several interrupts. So if you >> have any mac hardware at all with an SCC part you can test, it >> might be good to check that before committing. > > As it turns out, this description is not quite accurate -- it will > break devices with children with more than one interrupt. This > description fits SCC, where each child has three interrupts (one for > general stuff, and two for the DBDMA channels). Thus SCC channel B > is likely to stop working without some fixups to its interrupt > allocation on macio. I'll test the patch... -- Marcel Moolenaar xcllnt@mac.com
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