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Date:      Tue, 04 Feb 2003 14:28:38 -0500 (EST)
From:      John Baldwin <jhb@FreeBSD.org>
To:        Brendon and Wendy <brendy33@attbi.com>
Cc:        freebsd-smp@freebsd.org
Subject:   RE: mp_machdep.c patch
Message-ID:  <XFMail.20030204142838.jhb@FreeBSD.org>
In-Reply-To: <200302032001.23528.brendy33@attbi.com>

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On 04-Feb-2003 Brendon and Wendy wrote:
> Hi,
> 
> Saw the announce for the mp_machdep.c patch for hyperthreading. Installed, 
> built kernel and world. Everything seems fine.
> 
> Question - how does one determine whether the hyperthreading working? My DMESG 
> is below, as well as output from top. Booting with HTT disabled looks the 
> same to me.
> 
> This is on a supermicro p4dce+ (i860) with 2x HTT 2.0G xeons.
> 
> Cheers,
> Brendon
> 
> Copyright (c) 1992-2003 The FreeBSD Project.
> Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994
>         The Regents of the University of California. All rightands reserved.
> FreeBSD 4.7-STABLE #2: Mon Feb  3 18:35:10 PST 2003
>     root@bigboot.humphrey.world:/usr/obj/usr/src/sys/BRENDY-STABLE
> Timecounter "i8254"  frequency 1193182 Hz
> CPU: Intel(R) XEON(TM) CPU 2.00GHz (1982.52-MHz 686-class CPU)
>   Origin = "GenuineIntel"  Id = 0xf24  Stepping = 4
>   
> Features=0x3febfbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CLFLUS
> H,DTS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM>
>   Hyperthreading: 2 logical CPUs
> real memory  = 536805376 (524224K bytes)
> avail memory = 517742592 (505608K bytes)
> Programming 24 pins in IOAPIC #0
> IOAPIC #0 intpin 2 -> irq 0
> FreeBSD/SMP: Multiprocessor motherboard
>  cpu0 (BSP): apic id:  0, version: 0x00050014, at 0xfee00000
>  cpu1 (AP):  apic id:  1, version: 0x00050014, at 0xfee00000
>  io0 (APIC): apic id:  2, version: 0x00178020, at 0xfec00000

This set of APIC ID's is very odd and is your problem. :(  Is your
AP on apic id 1 when you booted up prior to having the HTT support?
My guess is that it is.  According to Intel, when you have HTT cores,
the APIC ID's of the cores in a physical processor are sequential.
The typical SMP + HTT setup I've seen is a physical cpu at ID 0
with it's 2nd core at ID 1 and the 2nd physical cpu at ID 6 with
it's 2nd core at ID 7.  The HTT core enumeration code assumes that
this is the case, and if it finds that any of the APIC ID's that
should be HTT cores are already in use by another physical CPU, it
doesn't turn on any of the HTT cores because it has no way of
talking to them. :)

My guess is that this is a problem with your motherboard.  You still
have SMP, but it is just with one core per processor.

-- 

John Baldwin <jhb@FreeBSD.org>  <><  http://www.FreeBSD.org/~jhb/
"Power Users Use the Power to Serve!"  -  http://www.FreeBSD.org/

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