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Date:      Fri, 28 Mar 2008 15:53:42 +0900
From:      Pyun YongHyeon <pyunyh@gmail.com>
To:        Danny Braniss <danny@cs.huji.ac.il>
Cc:        freebsd-stable@freebsd.org
Subject:   Re: Marvell Technology Group Ltd. Yukon EC Ultra
Message-ID:  <20080328065342.GG98450@cdnetworks.co.kr>
In-Reply-To: <E1Jeqev-000EQQ-RQ@cs1.cs.huji.ac.il>
References:  <E1JeqLf-000EDk-0z@cs1.cs.huji.ac.il> <20080327114712.GB95274@cdnetworks.co.kr> <E1Jeqev-000EQQ-RQ@cs1.cs.huji.ac.il>

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On Thu, Mar 27, 2008 at 01:52:41PM +0200, Danny Braniss wrote:
 > > On Thu, Mar 27, 2008 at 01:32:46PM +0200, Danny Braniss wrote:
 > >  > > On Thu, Mar 27, 2008 at 12:57:31PM +0200, Danny Braniss wrote:
 > >  > >  > Hi,
 > >  > >  > 	Under load, the msk has problems,  with hw.msk.legacy_intr=1 and 0.
 > >  > >  > with = 1, i get
 > >  > >  > 	TCP segementation error
 > >  > >  > 	watchdog timeout
 > >  > >  > with = 0,
 > >  > >  > 	Tx MAC parity error
 > >  > >  > 	watchdog timeout
 > >  > >  > 
 > >  > > 
 > >  > > Would you show me verbosed boot messages related with msk(4)/e1000phy(4)?
 > >  > >
 > >  > mskc0: <Marvell Yukon 88E8056 Gigabit Ethernet> port 0xc800-0xc8ff mem 
 > >  > 0xfeafc000-0xfeafffff irq 17 at device 0.0 on pci1
 > >  > mskc0: Reserved 0x4000 bytes for rid 0x10 type 3 at 0xfeafc000
 > >  > mskc0: MSI count : 1
 > >  > mskc0: attempting to allocate 1 MSI vectors (1 supported)
 > >  > msi: routing MSI IRQ 256 to vector 52
 > >  > mskc0: using IRQ 256 for MSI
 > >  > mskc0: RAM buffer size : 128KB
        ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

Hmm, I don't think EC Ultra have that much of RAM buffer.

 > >  > mskc0: Port 0 : Rx Queue 85KB(0x00000000:0x000153ff)
 > >  > mskc0: Port 0 : Tx Queue 43KB(0x00015400:0x0001ffff)
 > >  > msk0: <Marvell Technology Group Ltd. Yukon EC Ultra Id 0xb4 Rev 0x03> on mskc0
 > >  > msk0: bpf attached
 > >  > msk0: Ethernet address: 00:1e:8c:6d:5c:fe
 > >  > miibus0: <MII bus> on msk0
 > >  > e1000phy0: <Marvell 88E1149 Gigabit PHY> PHY 0 on miibus0
 > >  > e1000phy0:  10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseTX-FDX, 
 > >  > auto
 > >  > mskc0: [MPSAFE]
 > >  > mskc0: [FILTER]
 > >  > 
 > >  > is this enough?
 > > 
 > > Yes, it seems that 88E8056/88E1149 PHY has several issues. I recall
 > > that there had been several reports for this issue. Since nfe(4)
 > > with 88E1149 also have some stability issues, e1000phy(4) has lack
 > > of required code for 88E1149 PHY. Up to date, I couldn't find a
 > > clue, sorry. I'll let you know if I have a code to give it spin.
 > 
 > great and thanks,
 > 

Please try attached patch and let me know how it goes.

-- 
Regards,
Pyun YongHyeon

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--- sys/dev/msk/if_msk.c.orig	2008-03-27 13:43:51.000000000 +0900
+++ sys/dev/msk/if_msk.c	2008-03-28 15:17:44.000000000 +0900
@@ -1041,14 +1041,15 @@
 {
 	int next;
 	int i;
-	uint8_t val;
 
 	/* Get adapter SRAM size. */
-	val = CSR_READ_1(sc, B2_E_0);
-	sc->msk_ramsize = (val == 0) ? 128 : val * 4;
+	sc->msk_ramsize = CSR_READ_1(sc, B2_E_0) * 4;
 	if (bootverbose)
 		device_printf(sc->msk_dev,
 		    "RAM buffer size : %dKB\n", sc->msk_ramsize);
+
+	if (sc->msk_ramsize == 0)
+		return (0);
 	/*
 	 * Give receiver 2/3 of memory and round down to the multiple
 	 * of 1024. Tx/Rx RAM buffer size of Yukon II shoud be multiple
@@ -1116,8 +1117,6 @@
 		} else if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U) {
 			uint32_t our;
 
-			CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON);
-
 			/* Enable all clocks. */
 			pci_write_config(sc->msk_dev, PCI_OUR_REG_3, 0, 4);
 			our = pci_read_config(sc->msk_dev, PCI_OUR_REG_4, 4);
@@ -1125,8 +1124,14 @@
 			    PCI_ASPM_INT_FIFO_EMPTY|PCI_ASPM_CLKRUN_REQUEST);
 			/* Set all bits to 0 except bits 15..12. */
 			pci_write_config(sc->msk_dev, PCI_OUR_REG_4, our, 4);
-			/* Set to default value. */
-			pci_write_config(sc->msk_dev, PCI_OUR_REG_5, 0, 4);
+			/* Clear all bits to 0 except bits 28 & 27. */
+			our = pci_read_config(sc->msk_dev, PCI_OUR_REG_5, 4);
+			our &= ~(3 << 27);
+			pci_write_config(sc->msk_dev, PCI_OUR_REG_5, our, 4);
+			/* Workaround for status LE race. */
+			val = CSR_READ_4(sc, B2_GP_IO);
+			val |= 1 << 13;
+			CSR_WRITE_4(sc, B2_GP_IO, val);
 		}
 		/* Release PHY from PowerDown/COMA mode. */
 		pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4);
@@ -3677,21 +3682,28 @@
 	/* Configure hardware VLAN tag insertion/stripping. */
 	msk_setvlan(sc_if, ifp);
 
-	if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U) {
-		/* Set Rx Pause threshould. */
+	if (sc->msk_ramsize == 0) {
+		/* Set Rx Pause threshold. */
 		CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR),
 		    MSK_ECU_LLPP);
 		CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR),
 		    MSK_ECU_ULPP);
 		if (sc_if->msk_framesize > MSK_MAX_FRAMELEN) {
-			/*
-			 * Set Tx GMAC FIFO Almost Empty Threshold.
-			 */
-			CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR),
-			    MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR);
-			/* Disable Store & Forward mode for Tx. */
-			CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
-			    TX_JUMBO_ENA | TX_STFW_DIS);
+			if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U) {
+				/*
+				 * Set Tx GMAC FIFO Almost Empty Threshold.
+				 */
+				CSR_WRITE_4(sc,
+				    MR_ADDR(sc_if->msk_port,TX_GMF_AE_THR),
+				    MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR);
+				/* Disable Store & Forward mode for Tx. */
+				CSR_WRITE_4(sc,
+				    MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
+				    TX_JUMBO_ENA | TX_STFW_DIS);
+			} else
+				CSR_WRITE_4(sc,
+				    MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
+				    TX_JUMBO_ENA | TX_STFW_ENA);
 		} else {
 			/* Enable Store & Forward mode for Tx. */
 			CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
@@ -3790,6 +3802,8 @@
 	int ltpp, utpp;
 
 	sc = sc_if->msk_softc;
+	if (sc->msk_ramsize == 0)
+		return;
 
 	/* Setup Rx Queue. */
 	CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR);

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