Date: Fri, 28 Nov 2008 00:48:06 +0000 (UTC) From: Sam Leffler <sam@FreeBSD.org> To: src-committers@freebsd.org, svn-src-projects@freebsd.org Subject: svn commit: r185380 - in projects/ath_hal: . ar5210 ar5211 ar5212 ar5312 ar5416 Message-ID: <200811280048.mAS0m6hP002706@svn.freebsd.org>
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Author: sam Date: Fri Nov 28 00:48:05 2008 New Revision: 185380 URL: http://svn.freebsd.org/changeset/base/185380 Log: Update to later code from my repository: o many bug fixes o add new periodic calibration api o break up 5416 periodic calibration code in preparation for 928x o move get noise floor to rf backends o 5416-specific ani (still disabled) o modularize 5210 eeprom format a la other eeprom formats o start cleaning up regdomain code o prepare for proper 1/2 and 1/4 width channel support o bring back 900MHz card support o clean up 5212 rf version handling o add 1/2 and 1/4 width channel support for 5212 parts o split 5212 rfgain handling out o improve ani debugging o add AH_USE_INIPDGAIN compile option o purge a bunch of dead 5212 state o add 1/2 and 1/4 rate modes o remove HAL_CAP_CHAN_HALFRATE and HAL_CAP_CHAN_QUARTERRATE; the same info can now be deduced from the set of supported modes Added: projects/ath_hal/ah_eeprom_v1.c (contents, props changed) projects/ath_hal/ah_eeprom_v1.h (contents, props changed) projects/ath_hal/ar5212/ar5212_rfgain.c (contents, props changed) projects/ath_hal/ar5416/ar5416_ani.c (contents, props changed) projects/ath_hal/ar5416/ar5416_cal.c (contents, props changed) projects/ath_hal/ar5416/ar5416_cal.h (contents, props changed) projects/ath_hal/ar5416/ar5416_cal_adcdc.c (contents, props changed) projects/ath_hal/ar5416/ar5416_cal_adcgain.c (contents, props changed) projects/ath_hal/ar5416/ar5416_cal_iq.c (contents, props changed) Modified: projects/ath_hal/ah.c projects/ath_hal/ah.h projects/ath_hal/ah_desc.h projects/ath_hal/ah_devid.h projects/ath_hal/ah_eeprom.h projects/ath_hal/ah_eeprom_v14.c projects/ath_hal/ah_eeprom_v3.c projects/ath_hal/ah_internal.h projects/ath_hal/ah_regdomain.c projects/ath_hal/ar5210/ar5210.h projects/ath_hal/ar5210/ar5210_attach.c projects/ath_hal/ar5210/ar5210_misc.c projects/ath_hal/ar5210/ar5210_reset.c projects/ath_hal/ar5210/ar5210desc.h projects/ath_hal/ar5211/ar5211.h projects/ath_hal/ar5211/ar5211_attach.c projects/ath_hal/ar5211/ar5211_interrupts.c projects/ath_hal/ar5211/ar5211_misc.c projects/ath_hal/ar5211/ar5211_reset.c projects/ath_hal/ar5211/ar5211_xmit.c projects/ath_hal/ar5212/ar2316.c projects/ath_hal/ar5212/ar2317.c projects/ath_hal/ar5212/ar2413.c projects/ath_hal/ar5212/ar2425.c projects/ath_hal/ar5212/ar5212.h projects/ath_hal/ar5212/ar5212_ani.c projects/ath_hal/ar5212/ar5212_attach.c projects/ath_hal/ar5212/ar5212_interrupts.c projects/ath_hal/ar5212/ar5212_misc.c projects/ath_hal/ar5212/ar5212_phy.c projects/ath_hal/ar5212/ar5212_reset.c projects/ath_hal/ar5212/ar5212phy.h projects/ath_hal/ar5212/ar5212reg.h projects/ath_hal/ar5212/ar5311reg.h projects/ath_hal/ar5212/ar5413.c projects/ath_hal/ar5312/ar5312.h projects/ath_hal/ar5312/ar5312_attach.c projects/ath_hal/ar5312/ar5312_misc.c projects/ath_hal/ar5312/ar5312_reset.c projects/ath_hal/ar5416/ar2133.c projects/ath_hal/ar5416/ar5416.h projects/ath_hal/ar5416/ar5416_attach.c projects/ath_hal/ar5416/ar5416_beacon.c projects/ath_hal/ar5416/ar5416_misc.c projects/ath_hal/ar5416/ar5416_phy.c projects/ath_hal/ar5416/ar5416_power.c projects/ath_hal/ar5416/ar5416_recv.c projects/ath_hal/ar5416/ar5416_reset.c projects/ath_hal/ar5416/ar5416_xmit.c projects/ath_hal/ar5416/ar5416desc.h projects/ath_hal/ar5416/ar5416phy.h projects/ath_hal/ar5416/ar5416reg.h projects/ath_hal/ar5416/ar9160_attach.c projects/ath_hal/version.h Modified: projects/ath_hal/ah.c ============================================================================== --- projects/ath_hal/ah.c Fri Nov 28 00:17:12 2008 (r185379) +++ projects/ath_hal/ah.c Fri Nov 28 00:48:05 2008 (r185380) @@ -14,7 +14,7 @@ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * - * $Id: ah.c,v 1.13 2008/11/10 04:08:00 sam Exp $ + * $Id: ah.c,v 1.15 2008/11/15 22:15:44 sam Exp $ */ #include "opt_ah.h" @@ -46,6 +46,14 @@ extern struct ath_hal *ar5416Attach(uint extern struct ath_hal *ar9160Attach(uint16_t, HAL_SOFTC, HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS*); #endif +#ifdef AH_SUPPORT_AR9280 +extern struct ath_hal *ar9280Attach(uint16_t, HAL_SOFTC, + HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS*); +#endif +#ifdef AH_SUPPORT_AR9285 +extern struct ath_hal *ar9285Attach(uint16_t, HAL_SOFTC, + HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS*); +#endif #include "version.h" char ath_hal_version[] = ATH_HAL_VERSION; @@ -68,6 +76,12 @@ const char* ath_hal_buildopts[] = { #ifdef AH_SUPPORT_AR9180 "AR9180", #endif +#ifdef AH_SUPPORT_AR9280 + "AR9280", +#endif +#ifdef AH_SUPPORT_AR9285 + "AR9285", +#endif #ifdef AH_SUPPORT_5111 "RF5111", #endif @@ -110,12 +124,21 @@ const char* ath_hal_buildopts[] = { #ifdef AH_PRIVATE_DIAG "PRIVATE_DIAG", #endif +#ifdef AH_SUPPORT_WRITE_EEPROM + "WRITE_EEPROM", +#endif +#ifdef AH_SUPPORT_WRITE_REGDOMAIN + "WRITE_REGDOMAIN", +#endif #ifdef AH_DEBUG_COUNTRY "DEBUG_COUNTRY", #endif #ifdef AH_NEED_DESC_SWAP "TX_DESC_SWAP", #endif +#ifdef AH_USE_INIPDGAIN + "INIPDGAIN", +#endif #ifdef AH_DISABLE_WME "DISABLE_WME", #endif @@ -169,6 +192,11 @@ ath_hal_devname(uint16_t devid) return "Atheros 5416"; case AR9160_DEVID_PCI: return "Atheros 9160"; + case AR9280_DEVID_PCI: + case AR9280_DEVID_PCIE: + return "Atheros 9280"; + case AR9285_DEVID_PCIE: + return "Atheros 9285"; } return AH_NULL; } @@ -247,6 +275,17 @@ ath_hal_attach(uint16_t devid, HAL_SOFTC ah = ar9160Attach(devid, sc, st, sh, error); break; #endif +#ifdef AH_SUPPORT_AR9280 + case AR9280_DEVID_PCI: + case AR9280_DEVID_PCIE: + ah = ar9280Attach(devid, sc, st, sh, error); + break; +#endif +#ifdef AH_SUPPORT_AR9285 + case AR9285_DEVID_PCIE: + ah = ar9285Attach(devid, sc, st, sh, error); + break; +#endif default: ah = AH_NULL; *error = HAL_ENXIO; @@ -419,6 +458,19 @@ ath_hal_computetxtime(struct ath_hal *ah } static __inline int +mapgsm(u_int freq, u_int flags) +{ + freq *= 10; + if (flags & CHANNEL_QUARTER) + freq += 5; + else if (flags & CHANNEL_HALF) + freq += 10; + else + freq += 20; + return (freq - 24220) / 5; +} + +static __inline int mappsb(u_int freq, u_int flags) { return ((freq * 10) + (((freq % 5) == 2) ? 5 : 0) - 49400) / 5; @@ -434,6 +486,8 @@ ath_hal_mhz2ieee(struct ath_hal *ah, u_i if (freq == 2484) return 14; if (freq < 2484) { + if (ath_hal_isgsmsku(ah)) + return mapgsm(freq, flags); return ((int)freq - 2407) / 5; } else return 15 + ((freq - 2512) / 20); @@ -450,6 +504,8 @@ ath_hal_mhz2ieee(struct ath_hal *ah, u_i if (freq == 2484) return 14; if (freq < 2484) { + if (ath_hal_isgsmsku(ah)) + return mapgsm(freq, flags); return ((int)freq - 2407) / 5; } if (freq < 5000) { @@ -641,10 +697,6 @@ ath_hal_getcapability(struct ath_hal *ah return pCap->halMcastKeySrchSupport ? HAL_OK : HAL_ENOTSUPP; case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */ return HAL_ENOTSUPP; - case HAL_CAP_CHAN_HALFRATE: - return pCap->halChanHalfRate ? HAL_OK : HAL_ENOTSUPP; - case HAL_CAP_CHAN_QUARTERRATE: - return pCap->halChanQuarterRate ? HAL_OK : HAL_ENOTSUPP; case HAL_CAP_RFSILENT: /* rfsilent support */ switch (capability) { case 0: /* facility is supported */ @@ -789,6 +841,15 @@ ath_hal_getdiagstate(struct ath_hal *ah, if (argsize != sizeof(uint16_t)) return AH_FALSE; return ah->ah_resetKeyCacheEntry(ah, *(const uint16_t *)args); +#ifdef AH_SUPPORT_WRITE_EEPROM + case HAL_DIAG_EEWRITE: { + const HAL_DIAG_EEVAL *ee; + if (argsize != sizeof(HAL_DIAG_EEVAL)) + return AH_FALSE; + ee = (const HAL_DIAG_EEVAL *)args; + return ath_hal_eepromWrite(ah, ee->ee_off, ee->ee_data); + } +#endif /* AH_SUPPORT_WRITE_EEPROM */ #endif /* AH_PRIVATE_DIAG */ case HAL_DIAG_11NCOMPAT: if (argsize == 0) { Modified: projects/ath_hal/ah.h ============================================================================== --- projects/ath_hal/ah.h Fri Nov 28 00:17:12 2008 (r185379) +++ projects/ath_hal/ah.h Fri Nov 28 00:48:05 2008 (r185380) @@ -14,7 +14,7 @@ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * - * $Id: ah.h,v 1.13 2008/11/10 04:08:00 sam Exp $ + * $Id: ah.h,v 1.15 2008/11/15 03:43:50 sam Exp $ */ #ifndef _ATH_AH_H_ @@ -105,8 +105,8 @@ typedef enum { HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */ /* 21 was HAL_CAP_XR */ HAL_CAP_WME_TKIPMIC = 22, /* hardware can support TKIP MIC when WMM is turned on */ - HAL_CAP_CHAN_HALFRATE = 23, /* hardware can support half rate channels */ - HAL_CAP_CHAN_QUARTERRATE = 24, /* hardware can support quarter rate channels */ + /* 23 was HAL_CAP_CHAN_HALFRATE */ + /* 24 was HAL_CAP_CHAN_QUARTERRATE */ HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */ HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */ HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */ @@ -466,8 +466,10 @@ enum { #endif HAL_MODE_108G = 0x020, /* 11g+Turbo channels */ HAL_MODE_108A = 0x040, /* 11a+Turbo channels */ - HAL_MODE_11A_HALF_RATE = 0x200, /* 11A half rate channels */ - HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11A quarter rate channels */ + HAL_MODE_11A_HALF_RATE = 0x200, /* 11a half width channels */ + HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11a quarter width channels */ + HAL_MODE_11G_HALF_RATE = 0x800, /* 11g half width channels */ + HAL_MODE_11G_QUARTER_RATE = 0x1000, /* 11g quarter width channels */ HAL_MODE_11NG_HT20 = 0x008000, HAL_MODE_11NA_HT20 = 0x010000, HAL_MODE_11NG_HT40PLUS = 0x020000, @@ -654,7 +656,7 @@ struct ath_rx_status; struct ath_hal { uint32_t ah_magic; /* consistency check magic number */ uint32_t ah_abi; /* HAL ABI version */ -#define HAL_ABI_VERSION 0x08110600 /* YYMMDDnn */ +#define HAL_ABI_VERSION 0x08111400 /* YYMMDDnn */ uint16_t ah_devid; /* PCI device ID */ uint16_t ah_subvendorid; /* PCI subvendor ID */ HAL_SOFTC ah_sc; /* back pointer to driver/os state */ @@ -680,7 +682,11 @@ struct ath_hal { HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *); HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *); void __ahdecl(*ah_setPCUConfig)(struct ath_hal *); - HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*, HAL_CHANNEL *, HAL_BOOL *); + HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*, HAL_CHANNEL *, + HAL_BOOL *); + HAL_BOOL __ahdecl(*ah_perCalibrationN)(struct ath_hal *, HAL_CHANNEL *, + u_int chainMask, HAL_BOOL longCal, HAL_BOOL *isCalDone); + HAL_BOOL __ahdecl(*ah_resetCalValid)(struct ath_hal *, HAL_CHANNEL *); HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t); /* Transmit functions */ Modified: projects/ath_hal/ah_desc.h ============================================================================== --- projects/ath_hal/ah_desc.h Fri Nov 28 00:17:12 2008 (r185379) +++ projects/ath_hal/ah_desc.h Fri Nov 28 00:48:05 2008 (r185380) @@ -167,7 +167,8 @@ enum { /* * Definitions for the software frame/packet descriptors used by - * the Atheros HAL. Drivers are expected to fillin the + * the Atheros HAL. This definition obscures hardware-specific + * details from the driver. Drivers are expected to fillin the * portions of a descriptor that are not opaque then use HAL calls * to complete the work. Status for completed frames is returned * in a device-independent format. Modified: projects/ath_hal/ah_devid.h ============================================================================== --- projects/ath_hal/ah_devid.h Fri Nov 28 00:17:12 2008 (r185379) +++ projects/ath_hal/ah_devid.h Fri Nov 28 00:48:05 2008 (r185380) @@ -23,8 +23,8 @@ #define ATHEROS_VENDOR_ID 0x168c /* Atheros PCI vendor ID */ /* * NB: all Atheros-based devices should have a PCI vendor ID - * of 0x168c, but some vendors do not follow this so we - * must handle them specially. + * of 0x168c, but some vendors, in their infinite wisdom + * do not follow this so we must handle them specially. */ #define ATHEROS_3COM_VENDOR_ID 0xa727 /* 3Com 3CRPAG175 vendor ID */ #define ATHEROS_3COM2_VENDOR_ID 0x10b7 /* 3Com 3CRDAG675 vendor ID */ Modified: projects/ath_hal/ah_eeprom.h ============================================================================== --- projects/ath_hal/ah_eeprom.h Fri Nov 28 00:17:12 2008 (r185379) +++ projects/ath_hal/ah_eeprom.h Fri Nov 28 00:48:05 2008 (r185380) @@ -14,11 +14,12 @@ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * - * $Id: ah_eeprom.h,v 1.6 2008/11/10 04:08:00 sam Exp $ + * $Id: ah_eeprom.h,v 1.11 2008/11/27 22:32:48 sam Exp $ */ #ifndef _ATH_AH_EEPROM_H_ #define _ATH_AH_EEPROM_H_ +#define AR_EEPROM_VER1 0x1000 /* Version 1.0; 5210 only */ /* * Version 3 EEPROMs are all 16K. * 3.1 adds turbo limit, antenna gain, 16 CTL's, 11g info, @@ -34,15 +35,17 @@ #define AR_EEPROM_VER3_2 0x3002 /* Version 3.2 */ #define AR_EEPROM_VER3_3 0x3003 /* Version 3.3 */ #define AR_EEPROM_VER3_4 0x3004 /* Version 3.4 */ +#define AR_EEPROM_VER4 0x4000 /* Version 4.x */ #define AR_EEPROM_VER4_0 0x4000 /* Version 4.0 */ #define AR_EEPROM_VER4_1 0x4001 /* Version 4.0 */ #define AR_EEPROM_VER4_2 0x4002 /* Version 4.0 */ #define AR_EEPROM_VER4_3 0x4003 /* Version 4.0 */ #define AR_EEPROM_VER4_6 0x4006 /* Version 4.0 */ #define AR_EEPROM_VER4_7 0x3007 /* Version 4.7 */ -#define AR_EEPROM_VER4_9 0x4009 /* EEPROM EAR futureproofing */ -#define AR_EEPROM_VER5_0 0x5000 /* Adds new 2413 cal powers and added params */ -#define AR_EEPROM_VER5_1 0x5001 /* Adds capability values */ +#define AR_EEPROM_VER4_9 0x4009 /* EEPROM EAR futureproofing */ +#define AR_EEPROM_VER5 0x5000 /* Version 5.x */ +#define AR_EEPROM_VER5_0 0x5000 /* Adds new 2413 cal powers and added params */ +#define AR_EEPROM_VER5_1 0x5001 /* Adds capability values */ #define AR_EEPROM_VER5_3 0x5003 /* Adds spur mitigation table */ #define AR_EEPROM_VER5_4 0x5004 /* @@ -50,7 +53,8 @@ * 14.2 adds txFrameToPaOn, txFrameToDataStart, ht40PowerInc * 14.3 adds bswAtten, bswMargin, swSettle, and base OpFlags for HT20/40 */ -#define AR_EEPROM_VER14_1 0xE001 /* 11n support */ +#define AR_EEPROM_VER14 0xE000 /* Version 14.x */ +#define AR_EEPROM_VER14_1 0xE001 /* Adds 11n support */ #define AR_EEPROM_VER14_2 0xE002 #define AR_EEPROM_VER14_3 0xE003 #define AR_EEPROM_VER14_7 0xE007 @@ -75,8 +79,8 @@ enum { AR_EEP_BURST, /* use ath_hal_eepromGetFlag */ AR_EEP_MAXQCU, /* uint16_t* */ AR_EEP_KCENTRIES, /* uint16_t* */ - AR_EEP_NFTHRESH_5, /* uint8_t* */ - AR_EEP_NFTHRESH_2, /* uint8_t* */ + AR_EEP_NFTHRESH_5, /* int16_t* */ + AR_EEP_NFTHRESH_2, /* int16_t* */ AR_EEP_REGDMN_0, /* uint16_t* */ AR_EEP_REGDMN_1, /* uint16_t* */ AR_EEP_OPCAP, /* uint16_t* */ @@ -122,6 +126,8 @@ typedef struct { /* XXX exposed to chip code */ #define MAX_RATE_POWER 63 +HAL_STATUS ath_hal_v1EepromAttach(struct ath_hal *ah); HAL_STATUS ath_hal_legacyEepromAttach(struct ath_hal *ah); HAL_STATUS ath_hal_v14EepromAttach(struct ath_hal *ah); +HAL_STATUS ath_hal_v4kEepromAttach(struct ath_hal *ah); #endif /* _ATH_AH_EEPROM_H_ */ Added: projects/ath_hal/ah_eeprom_v1.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ projects/ath_hal/ah_eeprom_v1.c Fri Nov 28 00:48:05 2008 (r185380) @@ -0,0 +1,253 @@ +/* + * Copyright (c) 2008 Sam Leffler, Errno Consulting + * Copyright (c) 2008 Atheros Communications, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * $Id: ah_eeprom_v1.c,v 1.1 2008/11/11 02:40:11 sam Exp $ + */ +#include "opt_ah.h" + +#include "ah.h" +#include "ah_internal.h" +#include "ah_eeprom_v1.h" + +static HAL_STATUS +v1EepromGet(struct ath_hal *ah, int param, void *val) +{ + HAL_EEPROM_v1 *ee = AH_PRIVATE(ah)->ah_eeprom; + uint32_t sum; + uint16_t eeval; + uint8_t *macaddr; + int i; + + switch (param) { + case AR_EEP_MACADDR: /* Get MAC Address */ + sum = 0; + macaddr = val; + for (i = 0; i < 3; i++) { + if (!ath_hal_eepromRead(ah, AR_EEPROM_MAC(i), &eeval)) { + HALDEBUG(ah, HAL_DEBUG_ANY, + "%s: cannot read EEPROM location %u\n", + __func__, i); + return HAL_EEREAD; + } + sum += eeval; + macaddr[2*i + 0] = eeval >> 8; + macaddr[2*i + 1] = eeval & 0xff; + } + if (sum == 0 || sum == 0xffff*3) { + HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad mac address %s\n", + __func__, ath_hal_ether_sprintf(macaddr)); + return HAL_EEBADMAC; + } + return HAL_OK; + case AR_EEP_REGDMN_0: + *(uint16_t *) val = ee->ee_regDomain[0]; + return HAL_OK; + case AR_EEP_RFKILL: + HALASSERT(val == AH_NULL); + return ee->ee_rfKill ? HAL_OK : HAL_EIO; + case AR_EEP_WRITEPROTECT: + HALASSERT(val == AH_NULL); + return (ee->ee_protect & AR_EEPROM_PROTOTECT_WP_128_191) ? + HAL_OK : HAL_EIO; + default: + HALASSERT(0); + return HAL_EINVAL; + } +} + +static HAL_BOOL +v1EepromSet(struct ath_hal *ah, int param, int v) +{ + return HAL_EINVAL; +} + +static HAL_BOOL +v1EepromDiag(struct ath_hal *ah, int request, + const void *args, uint32_t argsize, void **result, uint32_t *resultsize) +{ + HAL_EEPROM_v1 *ee = AH_PRIVATE(ah)->ah_eeprom; + + switch (request) { + case HAL_DIAG_EEPROM: + *result = ee; + *resultsize = sizeof(*ee); + return AH_TRUE; + } + return AH_FALSE; +} + +static uint16_t +v1EepromGetSpurChan(struct ath_hal *ah, int ix, HAL_BOOL is2GHz) +{ + return AR_NO_SPUR; +} + +/* + * Reclaim any EEPROM-related storage. + */ +static void +v1EepromDetach(struct ath_hal *ah) +{ + HAL_EEPROM_v1 *ee = AH_PRIVATE(ah)->ah_eeprom; + + ath_hal_free(ee); + AH_PRIVATE(ah)->ah_eeprom = AH_NULL; +} + +HAL_STATUS +ath_hal_v1EepromAttach(struct ath_hal *ah) +{ + HAL_EEPROM_v1 *ee = AH_PRIVATE(ah)->ah_eeprom; + uint16_t athvals[AR_EEPROM_ATHEROS_MAX]; /* XXX off stack */ + uint16_t protect, version, eeval; + uint32_t sum; + int i, loc; + + HALASSERT(ee == AH_NULL); + + if (!ath_hal_eepromRead(ah, AR_EEPROM_MAGIC, &eeval)) { + HALDEBUG(ah, HAL_DEBUG_ANY, + "%s: cannot read EEPROM magic number\n", __func__); + return HAL_EEREAD; + } + if (eeval != 0x5aa5) { + HALDEBUG(ah, HAL_DEBUG_ANY, + "%s: invalid EEPROM magic number 0x%x\n", __func__, eeval); + return HAL_EEMAGIC; + } + + if (!ath_hal_eepromRead(ah, AR_EEPROM_PROTECT, &protect)) { + HALDEBUG(ah, HAL_DEBUG_ANY, + "%s: cannot read EEPROM protection bits; read locked?\n", + __func__); + return HAL_EEREAD; + } + HALDEBUG(ah, HAL_DEBUG_ATTACH, "EEPROM protect 0x%x\n", protect); + /* XXX check proper access before continuing */ + + if (!ath_hal_eepromRead(ah, AR_EEPROM_VERSION, &version)) { + HALDEBUG(ah, HAL_DEBUG_ANY, + "%s: unable to read EEPROM version\n", __func__); + return HAL_EEREAD; + } + if (((version>>12) & 0xf) != 1) { + /* + * This code only groks the version 1 EEPROM layout. + */ + HALDEBUG(ah, HAL_DEBUG_ANY, + "%s: unsupported EEPROM version 0x%x found\n", + __func__, version); + return HAL_EEVERSION; + } + + /* + * Read the Atheros EEPROM entries and calculate the checksum. + */ + sum = 0; + for (i = 0; i < AR_EEPROM_ATHEROS_MAX; i++) { + if (!ath_hal_eepromRead(ah, AR_EEPROM_ATHEROS(i), &athvals[i])) + return HAL_EEREAD; + sum ^= athvals[i]; + } + if (sum != 0xffff) { + HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad EEPROM checksum 0x%x\n", + __func__, sum); + return HAL_EEBADSUM; + } + + /* + * Valid checksum, fetch the regulatory domain and save values. + */ + if (!ath_hal_eepromRead(ah, AR_EEPROM_REG_DOMAIN, &eeval)) { + HALDEBUG(ah, HAL_DEBUG_ANY, + "%s: cannot read regdomain from EEPROM\n", __func__); + return HAL_EEREAD; + } + + ee = ath_hal_malloc(sizeof(HAL_EEPROM_v1)); + if (ee == AH_NULL) { + /* XXX message */ + return HAL_ENOMEM; + } + + ee->ee_version = version; + ee->ee_protect = protect; + ee->ee_antenna = athvals[2]; + ee->ee_biasCurrents = athvals[3]; + ee->ee_thresh62 = athvals[4] & 0xff; + ee->ee_xlnaOn = (athvals[4] >> 8) & 0xff; + ee->ee_xpaOn = athvals[5] & 0xff; + ee->ee_xpaOff = (athvals[5] >> 8) & 0xff; + ee->ee_regDomain[0] = (athvals[6] >> 8) & 0xff; + ee->ee_regDomain[1] = athvals[6] & 0xff; + ee->ee_regDomain[2] = (athvals[7] >> 8) & 0xff; + ee->ee_regDomain[3] = athvals[7] & 0xff; + ee->ee_rfKill = athvals[8] & 0x1; + ee->ee_devType = (athvals[8] >> 1) & 0x7; + + for (i = 0, loc = AR_EEPROM_ATHEROS_TP_SETTINGS; i < AR_CHANNELS_MAX; i++, loc += AR_TP_SETTINGS_SIZE) { + struct tpcMap *chan = &ee->ee_tpc[i]; + + /* Copy pcdac and gain_f values from EEPROM */ + chan->pcdac[0] = (athvals[loc] >> 10) & 0x3F; + chan->gainF[0] = (athvals[loc] >> 4) & 0x3F; + chan->pcdac[1] = ((athvals[loc] << 2) & 0x3C) + | ((athvals[loc+1] >> 14) & 0x03); + chan->gainF[1] = (athvals[loc+1] >> 8) & 0x3F; + chan->pcdac[2] = (athvals[loc+1] >> 2) & 0x3F; + chan->gainF[2] = ((athvals[loc+1] << 4) & 0x30) + | ((athvals[loc+2] >> 12) & 0x0F); + chan->pcdac[3] = (athvals[loc+2] >> 6) & 0x3F; + chan->gainF[3] = athvals[loc+2] & 0x3F; + chan->pcdac[4] = (athvals[loc+3] >> 10) & 0x3F; + chan->gainF[4] = (athvals[loc+3] >> 4) & 0x3F; + chan->pcdac[5] = ((athvals[loc+3] << 2) & 0x3C) + | ((athvals[loc+4] >> 14) & 0x03); + chan->gainF[5] = (athvals[loc+4] >> 8) & 0x3F; + chan->pcdac[6] = (athvals[loc+4] >> 2) & 0x3F; + chan->gainF[6] = ((athvals[loc+4] << 4) & 0x30) + | ((athvals[loc+5] >> 12) & 0x0F); + chan->pcdac[7] = (athvals[loc+5] >> 6) & 0x3F; + chan->gainF[7] = athvals[loc+5] & 0x3F; + chan->pcdac[8] = (athvals[loc+6] >> 10) & 0x3F; + chan->gainF[8] = (athvals[loc+6] >> 4) & 0x3F; + chan->pcdac[9] = ((athvals[loc+6] << 2) & 0x3C) + | ((athvals[loc+7] >> 14) & 0x03); + chan->gainF[9] = (athvals[loc+7] >> 8) & 0x3F; + chan->pcdac[10] = (athvals[loc+7] >> 2) & 0x3F; + chan->gainF[10] = ((athvals[loc+7] << 4) & 0x30) + | ((athvals[loc+8] >> 12) & 0x0F); + + /* Copy Regulatory Domain and Rate Information from EEPROM */ + chan->rate36 = (athvals[loc+8] >> 6) & 0x3F; + chan->rate48 = athvals[loc+8] & 0x3F; + chan->rate54 = (athvals[loc+9] >> 10) & 0x3F; + chan->regdmn[0] = (athvals[loc+9] >> 4) & 0x3F; + chan->regdmn[1] = ((athvals[loc+9] << 2) & 0x3C) + | ((athvals[loc+10] >> 14) & 0x03); + chan->regdmn[2] = (athvals[loc+10] >> 8) & 0x3F; + chan->regdmn[3] = (athvals[loc+10] >> 2) & 0x3F; + } + + AH_PRIVATE(ah)->ah_eeprom = ee; + AH_PRIVATE(ah)->ah_eeversion = version; + AH_PRIVATE(ah)->ah_eepromDetach = v1EepromDetach; + AH_PRIVATE(ah)->ah_eepromGet = v1EepromGet; + AH_PRIVATE(ah)->ah_eepromSet = v1EepromSet; + AH_PRIVATE(ah)->ah_getSpurChan = v1EepromGetSpurChan; + AH_PRIVATE(ah)->ah_eepromDiag = v1EepromDiag; + return HAL_OK; +} Added: projects/ath_hal/ah_eeprom_v1.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ projects/ath_hal/ah_eeprom_v1.h Fri Nov 28 00:48:05 2008 (r185380) @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting + * Copyright (c) 2002-2008 Atheros Communications, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * $Id: ah_eeprom_v1.h,v 1.1 2008/11/11 02:40:11 sam Exp $ + */ +#ifndef _ATH_AH_EEPROM_V1_H_ +#define _ATH_AH_EEPROM_V1_H_ + +#include "ah_eeprom.h" + +/* + * EEPROM defines for Version 1 Crete EEPROM. + * + * The EEPROM is segmented into three sections: + * + * PCI/Cardbus default configuration settings + * Cardbus CIS tuples and vendor-specific data + * Atheros-specific data + * + * EEPROM entries are read 32-bits at a time through the PCI bus + * interface but are all 16-bit values. + * + * Access to the Atheros-specific data is controlled by protection + * bits and the data is checksum'd. The driver reads the Atheros + * data from the EEPROM at attach and caches it in its private state. + * This data includes the local regulatory domain, channel calibration + * settings, and phy-related configuration settings. + */ +#define AR_EEPROM_MAC(i) (0x1f-(i))/* MAC address word */ +#define AR_EEPROM_MAGIC 0x3d /* magic number */ +#define AR_EEPROM_PROTECT 0x3f /* Atheros segment protect register */ +#define AR_EEPROM_PROTOTECT_WP_128_191 0x80 +#define AR_EEPROM_REG_DOMAIN 0xbf /* Current regulatory domain register */ +#define AR_EEPROM_ATHEROS_BASE 0xc0 /* Base of Atheros-specific data */ +#define AR_EEPROM_ATHEROS_MAX 64 /* 64x2=128 bytes of EEPROM settings */ +#define AR_EEPROM_ATHEROS(n) (AR_EEPROM_ATHEROS_BASE+(n)) +#define AR_EEPROM_VERSION AR_EEPROM_ATHEROS(1) +#define AR_EEPROM_ATHEROS_TP_SETTINGS 0x09 /* Transmit power settings */ +#define AR_REG_DOMAINS_MAX 4 /* # of Regulatory Domains */ +#define AR_CHANNELS_MAX 5 /* # of Channel calibration groups */ +#define AR_TP_SETTINGS_SIZE 11 /* # locations/Channel group */ +#define AR_TP_SCALING_ENTRIES 11 /* # entries in transmit power dBm->pcdac */ + +/* + * NB: we store the rfsilent select+polarity data packed + * with the encoding used in later parts so values + * returned to applications are consistent. + */ +#define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c +#define AR_EEPROM_RFSILENT_GPIO_SEL_S 2 +#define AR_EEPROM_RFSILENT_POLARITY 0x0002 +#define AR_EEPROM_RFSILENT_POLARITY_S 1 + +#define AR_I2DBM(x) ((uint8_t)((x * 2) + 3)) + +/* + * Transmit power and channel calibration settings. + */ +struct tpcMap { + uint8_t pcdac[AR_TP_SCALING_ENTRIES]; + uint8_t gainF[AR_TP_SCALING_ENTRIES]; + uint8_t rate36; + uint8_t rate48; + uint8_t rate54; + uint8_t regdmn[AR_REG_DOMAINS_MAX]; +}; + +/* + * Information retrieved from EEPROM. + */ +typedef struct { + uint16_t ee_version; /* Version field */ + uint16_t ee_protect; /* EEPROM protect field */ + uint16_t ee_antenna; /* Antenna Settings */ + uint16_t ee_biasCurrents; /* OB, DB */ + uint8_t ee_thresh62; /* thresh62 */ + uint8_t ee_xlnaOn; /* External LNA timing */ + uint8_t ee_xpaOff; /* Extern output stage timing */ + uint8_t ee_xpaOn; /* Extern output stage timing */ + uint8_t ee_rfKill; /* Single low bit signalling if RF Kill is implemented */ + uint8_t ee_devType; /* Type: PCI, miniPCI, CB */ + uint8_t ee_regDomain[AR_REG_DOMAINS_MAX]; + /* calibrated reg domains */ + struct tpcMap ee_tpc[AR_CHANNELS_MAX]; +} HAL_EEPROM_v1; +#endif /* _ATH_AH_EEPROM_V1_H_ */ Modified: projects/ath_hal/ah_eeprom_v14.c ============================================================================== --- projects/ath_hal/ah_eeprom_v14.c Fri Nov 28 00:17:12 2008 (r185379) +++ projects/ath_hal/ah_eeprom_v14.c Fri Nov 28 00:48:05 2008 (r185380) @@ -14,7 +14,7 @@ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * - * $Id: ah_eeprom_v14.c,v 1.3 2008/11/10 04:08:00 sam Exp $ + * $Id: ah_eeprom_v14.c,v 1.4 2008/11/10 19:04:26 sam Exp $ */ #include "opt_ah.h" @@ -37,10 +37,10 @@ v14EepromGet(struct ath_hal *ah, int par switch (param) { case AR_EEP_NFTHRESH_5: - *(int8_t *)val = pModal[0].noiseFloorThreshCh[0]; + *(int16_t *)val = pModal[0].noiseFloorThreshCh[0]; return HAL_OK; case AR_EEP_NFTHRESH_2: - *(int8_t *)val = pModal[1].noiseFloorThreshCh[0]; + *(int16_t *)val = pModal[1].noiseFloorThreshCh[0]; return HAL_OK; case AR_EEP_MACADDR: /* Get MAC Address */ sum = 0; Modified: projects/ath_hal/ah_eeprom_v3.c ============================================================================== --- projects/ath_hal/ah_eeprom_v3.c Fri Nov 28 00:17:12 2008 (r185379) +++ projects/ath_hal/ah_eeprom_v3.c Fri Nov 28 00:48:05 2008 (r185380) @@ -14,7 +14,7 @@ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * - * $Id: ah_eeprom_v3.c,v 1.3 2008/11/10 04:08:00 sam Exp $ + * $Id: ah_eeprom_v3.c,v 1.4 2008/11/27 22:39:42 sam Exp $ */ #include "opt_ah.h" @@ -1765,9 +1765,8 @@ legacyEepromDetach(struct ath_hal *ah) } /* - * TODO: Need to talk to Praveen about this, these are - * not valid 2.4 channels, either we change these - * or I need to change the beanie coding to accept these + * These are not valid 2.4 channels, either we change 'em + * or we need to change the coding to accept them. */ static const uint16_t channels11b[] = { 2412, 2447, 2484 }; static const uint16_t channels11g[] = { 2312, 2412, 2484 }; Modified: projects/ath_hal/ah_internal.h ============================================================================== --- projects/ath_hal/ah_internal.h Fri Nov 28 00:17:12 2008 (r185379) +++ projects/ath_hal/ah_internal.h Fri Nov 28 00:48:05 2008 (r185380) @@ -14,7 +14,7 @@ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * - * $Id: ah_internal.h,v 1.17 2008/11/10 04:08:00 sam Exp $ + * $Id: ah_internal.h,v 1.21 2008/11/27 22:29:27 sam Exp $ */ #ifndef _ATH_AH_INTERAL_H_ #define _ATH_AH_INTERAL_H_ @@ -66,6 +66,9 @@ typedef struct { /* * Transmit power scale factor. + * + * NB: This is not public because we want to discourage the use of + * scaling; folks should use the tx power limit interface. */ typedef enum { HAL_TP_SCALE_MAX = 0, /* no scaling (default) */ @@ -165,7 +168,23 @@ typedef struct { /* * The ``private area'' follows immediately after the ``public area'' - * in the data structure returned by ath_hal_attach. + * in the data structure returned by ath_hal_attach. Private data are + * used by device-independent code such as the regulatory domain support. + * In general, code within the HAL should never depend on data in the + * public area. Instead any public data needed internally should be + * shadowed here. + * + * When declaring a device-specific ath_hal data structure this structure + * is assumed to at the front; e.g. + * + * struct ath_hal_5212 { + * struct ath_hal_private ah_priv; + * ... + * }; + * + * It might be better to manage the method pointers in this structure + * using an indirect pointer to a read-only data structure but this would + * disallow class-style method overriding. */ struct ath_hal_private { struct ath_hal h; /* public area */ @@ -189,6 +208,8 @@ struct ath_hal_private { HAL_CHANNEL *, uint32_t); int16_t (*ah_getNfAdjust)(struct ath_hal *, const HAL_CHANNEL_INTERNAL*); + void (*ah_getNoiseFloor)(struct ath_hal *, + int16_t nfarray[]); void *ah_eeprom; /* opaque EEPROM state */ uint16_t ah_eeversion; /* EEPROM version */ @@ -267,6 +288,8 @@ struct ath_hal_private { AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chans, _nchan) #define ath_hal_getNfAdjust(_ah, _c) \ AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c) +#define ath_hal_getNoiseFloor(_ah, _nfArray) \ + AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray) #define ath_hal_eepromDetach(_ah) \ AH_PRIVATE(_ah)->ah_eepromDetach(_ah) Modified: projects/ath_hal/ah_regdomain.c ============================================================================== --- projects/ath_hal/ah_regdomain.c Fri Nov 28 00:17:12 2008 (r185379) +++ projects/ath_hal/ah_regdomain.c Fri Nov 28 00:48:05 2008 (r185380) @@ -15,7 +15,7 @@ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * - * $Id: ah_regdomain.c,v 1.17 2008/11/10 04:08:00 sam Exp $ + * $Id: ah_regdomain.c,v 1.24 2008/11/27 22:29:27 sam Exp $ */ #include "opt_ah.h" @@ -37,47 +37,49 @@ /* 10MHz is half the 11A bandwidth used to determine upper edge freq of the outdoor channel */ #define HALF_MAXCHANBW 10 - -/* - * Used to set the RegDomain bitmask which chooses which frequency - * band specs are used. - */ -#define BMLEN 2 /* Use 2 64 bit uint for channel bitmask - NB: Must agree with macro below (BM) */ -#define BMZERO {(uint64_t) 0, (uint64_t) 0} /* BMLEN zeros */ - -#define BM(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh, _fi, _fj, _fk, _fl) \ - {((((_fa >= 0) && (_fa < 64)) ? (((uint64_t) 1) << _fa) : (uint64_t) 0) | \ - (((_fb >= 0) && (_fb < 64)) ? (((uint64_t) 1) << _fb) : (uint64_t) 0) | \ - (((_fc >= 0) && (_fc < 64)) ? (((uint64_t) 1) << _fc) : (uint64_t) 0) | \ - (((_fd >= 0) && (_fd < 64)) ? (((uint64_t) 1) << _fd) : (uint64_t) 0) | \ - (((_fe >= 0) && (_fe < 64)) ? (((uint64_t) 1) << _fe) : (uint64_t) 0) | \ - (((_ff >= 0) && (_ff < 64)) ? (((uint64_t) 1) << _ff) : (uint64_t) 0) | \ - (((_fg >= 0) && (_fg < 64)) ? (((uint64_t) 1) << _fg) : (uint64_t) 0) | \ - (((_fh >= 0) && (_fh < 64)) ? (((uint64_t) 1) << _fh) : (uint64_t) 0) | \ - (((_fi >= 0) && (_fi < 64)) ? (((uint64_t) 1) << _fi) : (uint64_t) 0) | \ - (((_fj >= 0) && (_fj < 64)) ? (((uint64_t) 1) << _fj) : (uint64_t) 0) | \ - (((_fk >= 0) && (_fk < 64)) ? (((uint64_t) 1) << _fk) : (uint64_t) 0) | \ - (((_fl >= 0) && (_fl < 64)) ? (((uint64_t) 1) << _fl) : (uint64_t) 0) | \ - ((((_fa > 63) && (_fa < 128)) ? (((uint64_t) 1) << (_fa - 64)) : (uint64_t) 0) | \ - (((_fb > 63) && (_fb < 128)) ? (((uint64_t) 1) << (_fb - 64)) : (uint64_t) 0) | \ - (((_fc > 63) && (_fc < 128)) ? (((uint64_t) 1) << (_fc - 64)) : (uint64_t) 0) | \ - (((_fd > 63) && (_fd < 128)) ? (((uint64_t) 1) << (_fd - 64)) : (uint64_t) 0) | \ - (((_fe > 63) && (_fe < 128)) ? (((uint64_t) 1) << (_fe - 64)) : (uint64_t) 0) | \ - (((_ff > 63) && (_ff < 128)) ? (((uint64_t) 1) << (_ff - 64)) : (uint64_t) 0) | \ - (((_fg > 63) && (_fg < 128)) ? (((uint64_t) 1) << (_fg - 64)) : (uint64_t) 0) | \ - (((_fh > 63) && (_fh < 128)) ? (((uint64_t) 1) << (_fh - 64)) : (uint64_t) 0) | \ - (((_fi > 63) && (_fi < 128)) ? (((uint64_t) 1) << (_fi - 64)) : (uint64_t) 0) | \ - (((_fj > 63) && (_fj < 128)) ? (((uint64_t) 1) << (_fj - 64)) : (uint64_t) 0) | \ - (((_fk > 63) && (_fk < 128)) ? (((uint64_t) 1) << (_fk - 64)) : (uint64_t) 0) | \ - (((_fl > 63) && (_fl < 128)) ? (((uint64_t) 1) << (_fl - 64)) : (uint64_t) 0)))} +/* + * BMLEN defines the size of the bitmask used to hold frequency + * band specifications. Note this must agree with the BM macro + * definition that's used to setup initializers. See also further + * comments below. + */ +#define BMLEN 2 /* 2 x 64 bits in each channel bitmask */ +typedef uint64_t chanbmask_t[BMLEN]; + +#define W0(_a) \ + (((_a) >= 0 && (_a) < 64 ? (((uint64_t) 1)<<(_a)) : (uint64_t) 0)) +#define W1(_a) \ + (((_a) > 63 && (_a) < 128 ? (((uint64_t) 1)<<((_a)-64)) : (uint64_t) 0)) +#define BM1(_fa) { W0(_fa), W1(_fa) } +#define BM2(_fa, _fb) { W0(_fa) | W0(_fb), W1(_fa) | W1(_fb) } +#define BM3(_fa, _fb, _fc) \ + { W0(_fa) | W0(_fb) | W0(_fc), W1(_fa) | W1(_fb) | W1(_fc) } +#define BM4(_fa, _fb, _fc, _fd) \ + { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd), \ + W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) } +#define BM5(_fa, _fb, _fc, _fd, _fe) \ + { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe), \ + W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) } +#define BM6(_fa, _fb, _fc, _fd, _fe, _ff) \ + { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe) | W0(_ff), \ + W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) } +#define BM7(_fa, _fb, _fc, _fd, _fe, _ff, _fg) \ + { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe) | W0(_ff) | \ + W0(_fg),\ + W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) | \ + W1(_fg) } +#define BM8(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh) \ + { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe) | W0(_ff) | \ + W0(_fg) | W0(_fh) , \ + W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) | \ + W1(_fg) | W1(_fh) } /* * Country/Region Codes * Numbering from ISO 3166 */ -enum CountryCode { +enum { CTRY_ALBANIA = 8, /* Albania */ CTRY_ALGERIA = 12, /* Algeria */ CTRY_ARGENTINA = 32, /* Argentina */ @@ -202,6 +204,7 @@ enum CountryCode { CTRY_SLOVENIA = 705, /* Slovenia */ CTRY_SOUTH_AFRICA = 710, /* South Africa */ CTRY_SPAIN = 724, /* Spain */ + CTRY_SR9 = 5000, /* Ubiquiti SR9 (900MHz/GSM) */ CTRY_SWEDEN = 752, /* Sweden */ CTRY_SWITZERLAND = 756, /* Switzerland */ CTRY_SYRIA = 760, /* Syria */ @@ -219,23 +222,25 @@ enum CountryCode { CTRY_UZBEKISTAN = 860, /* Uzbekistan */ CTRY_VENEZUELA = 862, /* Venezuela */ CTRY_VIET_NAM = 704, /* Viet Nam */ + CTRY_XR9 = 5001, /* Ubiquiti XR9 (900MHz/GSM) */ + CTRY_GZ901 = 5002, /* Zcomax GZ-901 (900MHz/GSM) */ CTRY_YEMEN = 887, /* Yemen */ CTRY_ZIMBABWE = 716 /* Zimbabwe */ }; -/* Mask to check whether a domain is a multidomain or a single - domain */ - +/* + * Mask to check whether a domain is a multidomain or a single domain + */ #define MULTI_DOMAIN_MASK 0xFF00 -/* Enumerated Regulatory Domain Information 8 bit values indicate that +/* + * Enumerated Regulatory Domain Information 8 bit values indicate that * the regdomain is really a pair of unitary regdomains. 12 bit values * are the real unitary regdomains and are the only ones which have the * frequency bitmasks and flags set. */ - -enum EnumRd { +enum { /* * The following regulatory domain definitions are * found in the EEPROM. Each regulatory domain @@ -253,6 +258,7 @@ enum EnumRd { FCC1_FCCA = 0x10, /* USA */ FCC1_WORLD = 0x11, /* Hong Kong */ FCC4_FCCA = 0x12, /* USA - Public Safety */ + FCC5_FCCB = 0x13, /* USA w/ 1/2 and 1/4 width channels */ FCC2_FCCA = 0x20, /* Canada */ FCC2_WORLD = 0x21, /* Australia & HK */ @@ -380,7 +386,9 @@ enum EnumRd { FCC2 = 0x0120, /* Canada, Australia & New Zealand */ FCC3 = 0x0160, /* US w/new middle band & DFS */ FCC4 = 0x0165, /* US Public Safety */ + FCC5 = 0x0166, /* US w/ 1/2 and 1/4 width channels */ FCCA = 0x0A10, + FCCB = 0x0A11, /* US w/ 1/2 and 1/4 width channels */ APLD = 0x0D50, /* South Korea */ @@ -399,6 +407,9 @@ enum EnumRd { NULL1 = 0x0198, WORLD = 0x0199, + SR9_WORLD = 0x0298, + XR9_WORLD = 0x0299, + GZ901_WORLD = 0x029a, DEBUG_REG_DMN = 0x01ff, }; @@ -414,30 +425,24 @@ enum { /* conformance test limits */ /* * The following are flags for different requirements per reg domain. * These requirements are either inhereted from the reg domain pair or - * from the unitary reg domain if the reg domain pair flags value is - * 0 + * from the unitary reg domain if the reg domain pair flags value is 0 */ - enum { - NO_REQ = 0x00000000, + NO_REQ = 0x00000000, /* NB: must be zero */ DISALLOW_ADHOC_11A = 0x00000001, DISALLOW_ADHOC_11A_TURB = 0x00000002, NEED_NFC = 0x00000004, - ADHOC_PER_11D = 0x00000008, /* Start Ad-Hoc mode */ ADHOC_NO_11A = 0x00000010, - - PUBLIC_SAFETY_DOMAIN = 0x00000020, /* public safety domain */ - LIMIT_FRAME_4MS = 0x00000040, /* 4msec limit on the frame length */ - - NO_HOSTAP = 0x00000080, /* No HOSTAP mode opereation */ + LIMIT_FRAME_4MS = 0x00000020, /* 4msec limit on frame length*/ + NO_HOSTAP = 0x00000040, /* No HOSTAP mode opereation */ }; /* * The following describe the bit masks for different passive scan * capability/requirements per regdomain. */ -#define NO_PSCAN 0x0ULL +#define NO_PSCAN 0x0ULL /* NB: must be zero */ #define PSCAN_FCC 0x0000000000000001ULL #define PSCAN_FCC_T 0x0000000000000002ULL #define PSCAN_ETSI 0x0000000000000004ULL @@ -461,8 +466,7 @@ enum { * THE following table is the mapping of regdomain pairs specified by * an 8 bit regdomain value to the individual unitary reg domains */ - -typedef struct reg_dmn_pair_mapping { +typedef struct { HAL_REG_DOMAIN regDmnEnum; /* 16 bit reg domain pair */ HAL_REG_DOMAIN regDmn5GHz; /* 5GHz reg domain */ HAL_REG_DOMAIN regDmn2GHz; /* 2GHz reg domain */ @@ -487,12 +491,13 @@ static REG_DMN_PAIR_MAPPING regDomainPai {NULL1_ETSIB, NULL1, ETSIB, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, {NULL1_ETSIC, NULL1, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, - {FCC2_FCCA, FCC2, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, + {FCC2_FCCA, FCC2, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, {FCC2_WORLD, FCC2, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, {FCC2_ETSIC, FCC2, ETSIC, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, - {FCC3_FCCA, FCC3, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, - {FCC3_WORLD, FCC3, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, - {FCC4_FCCA, FCC4, FCCA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, + {FCC3_FCCA, FCC3, FCCA, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, + {FCC3_WORLD, FCC3, WORLD, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, + {FCC4_FCCA, FCC4, FCCA, DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB, NO_REQ, PSCAN_DEFER, 0 }, + {FCC5_FCCB, FCC5, FCCB, NO_REQ, NO_REQ, PSCAN_DEFER, 0 }, *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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