Date: Tue, 23 Jun 2009 11:34:46 -0700 (PDT) From: Neelkanth Natu <neelnatu@yahoo.com> To: freebsd-mips@freebsd.org Subject: Simple diff required for booting on MALTA Message-ID: <618819.81685.qm@web34404.mail.mud.yahoo.com>
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[-- Attachment #1 --]
Hi,
I am attaching a couple of simple diffs I had to make to get the mips
port booted on MALTA hardware with a MIPS 4Kc processor.
The change to uart_cpu_maltausart.c is to retain the baudrate set up by
YAMON instead of hardcoding it to 115200 (the baudrate set up by YAMON
is 38400).
The change to malta_machdep.c is to make sure that we call mips_timer_early_init() before the first write to console. This is necessary because the ns8250 driver calls DELAY() and without this change we hit a
divide-by-zero error.
Can somebody review these changes and commit them if they look alright?
best
Neel
[-- Attachment #2 --]
==== //depot/user/neelnatu/freebsd_sibyte/src/sys/mips/malta/uart_cpu_maltausart.c#4 - /u/neelnatu/p4/freebsd_sibyte/src/sys/mips/malta/uart_cpu_maltausart.c ====
@@ -70,7 +70,7 @@
di->bas.bst = 0;
di->bas.regshft = 0;
di->bas.rclk = 0;
- di->baudrate = 115200;
+ di->baudrate = 0; /* retain the baudrate configured by YAMON */
di->databits = 8;
di->stopbits = 1;
di->parity = UART_PARITY_NONE;
==== //depot/user/neelnatu/freebsd_sibyte/src/sys/mips/malta/malta_machdep.c#2 - /u/neelnatu/p4/freebsd_sibyte/src/sys/mips/malta/malta_machdep.c ====
@@ -226,6 +226,52 @@
}
+static uint64_t
+malta_cpu_speed(void)
+{
+ uint64_t platform_counter_freq = 0;
+
+#if defined(TICK_USE_YAMON_FREQ)
+ /*
+ * If we are running on a board which uses YAMON firmware,
+ * then query CPU pipeline clock from the syscon object.
+ * If unsuccessful, use hard-coded default.
+ */
+ platform_counter_freq = yamon_getcpufreq();
+
+#elif defined(TICK_USE_MALTA_RTC)
+ /*
+ * If we are running on a board with the MC146818 RTC,
+ * use it to determine CPU pipeline clock frequency.
+ */
+ u_int64_t counterval[2];
+
+ /* Set RTC to binary mode. */
+ writertc(RTC_STATUSB, (rtcin(RTC_STATUSB) | RTCSB_BCD));
+
+ /* Busy-wait for falling edge of RTC update. */
+ while (((rtcin(RTC_STATUSA) & RTCSA_TUP) == 0))
+ ;
+ while (((rtcin(RTC_STATUSA)& RTCSA_TUP) != 0))
+ ;
+ counterval[0] = mips_rd_count();
+
+ /* Busy-wait for falling edge of RTC update. */
+ while (((rtcin(RTC_STATUSA) & RTCSA_TUP) == 0))
+ ;
+ while (((rtcin(RTC_STATUSA)& RTCSA_TUP) != 0))
+ ;
+ counterval[1] = mips_rd_count();
+
+ platform_counter_freq = counterval[1] - counterval[0];
+#endif
+
+ if (platform_counter_freq == 0)
+ platform_counter_freq = MIPS_DEFAULT_HZ;
+
+ return (platform_counter_freq);
+}
+
void
platform_start(__register_t a0, __register_t a1, __register_t a2,
__register_t a3)
@@ -242,6 +288,9 @@
kernend = round_page((vm_offset_t)&end);
memset(&edata, 0, kernend - (vm_offset_t)(&edata));
+ platform_counter_freq = malta_cpu_speed();
+ mips_timer_early_init(platform_counter_freq);
+
cninit();
printf("entry: platform_start()\n");
@@ -262,44 +311,5 @@
realmem = btoc(memsize);
mips_init();
- do {
-#if defined(TICK_USE_YAMON_FREQ)
- /*
- * If we are running on a board which uses YAMON firmware,
- * then query CPU pipeline clock from the syscon object.
- * If unsuccessful, use hard-coded default.
- */
- platform_counter_freq = yamon_getcpufreq();
- if (platform_counter_freq == 0)
- platform_counter_freq = MIPS_DEFAULT_HZ;
-
-#elif defined(TICK_USE_MALTA_RTC)
- /*
- * If we are running on a board with the MC146818 RTC,
- * use it to determine CPU pipeline clock frequency.
- */
- u_int64_t counterval[2];
-
- /* Set RTC to binary mode. */
- writertc(RTC_STATUSB, (rtcin(RTC_STATUSB) | RTCSB_BCD));
-
- /* Busy-wait for falling edge of RTC update. */
- while (((rtcin(RTC_STATUSA) & RTCSA_TUP) == 0))
- ;
- while (((rtcin(RTC_STATUSA)& RTCSA_TUP) != 0))
- ;
- counterval[0] = mips_rd_count();
-
- /* Busy-wait for falling edge of RTC update. */
- while (((rtcin(RTC_STATUSA) & RTCSA_TUP) == 0))
- ;
- while (((rtcin(RTC_STATUSA)& RTCSA_TUP) != 0))
- ;
- counterval[1] = mips_rd_count();
-
- platform_counter_freq = counterval[1] - counterval[0];
-#endif
- } while(0);
-
mips_timer_init_params(platform_counter_freq, 0);
}
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