Date: Sun, 09 Aug 2009 18:50:19 -0700 From: Oleksandr Tymoshenko <gonzo@bluezbox.com> To: Neelkanth Natu <neelnatu@yahoo.com> Cc: freebsd-mips@freebsd.org Subject: Re: Diffs to fix L1 cache flush problems Message-ID: <4A7F7CDB.2030009@bluezbox.com> In-Reply-To: <153254.15259.qm@web34402.mail.mud.yahoo.com> References: <153254.15259.qm@web34402.mail.mud.yahoo.com>
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Neelkanth Natu wrote:
> Hi,
>
> This is a simple change that fixes problems invalidating L1
> data/instruction caches. The problem is that the type of the variable
> that holds the size of the instruction/data caches is uint8_t. Clearly
> this is going to overflow.
>
> On the Sibyte with 32KB cache size the uint8_t was causing it to be
> truncated to 0. This in turn makes the cache flush routines turn into
> no-ops.
>
> I ran into this when testing kernel loadable modules and have verified that
> this change fixes the problem.
Thanks, committed.
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