Date: Mon, 17 May 2010 20:03:12 +0530 From: "C. Jayachandran" <c.jayachandran@gmail.com> To: Neel Natu <neelnatu@gmail.com> Cc: freebsd-mips@freebsd.org Subject: Minor fixup for the MIPS SMP platform code. Message-ID: <AANLkTikjF2SUa5GomVRtus176hjKyUyPAeDF-p1kwCcO@mail.gmail.com>
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[-- Attachment #1 --] The attached patch (also at http://sites.google.com/site/cjayachandran/files) has two changes: - moves the intr masking code to platform_init_ap, so that we can avoid the #ifdef for XLR - adds a platform_smp_topo() function so that platforms can define their topology I've also attempted to fixup sys/mips/sibyte to reflect these changes, but it might need further work. sys/mips/cavium also might need similar changes for SMP. Please review and apply if the changes are okay. Thanks, JC. [-- Attachment #2 --] Index: sys/mips/sibyte/sb_machdep.c =================================================================== --- sys/mips/sibyte/sb_machdep.c (revision 208183) +++ sys/mips/sibyte/sb_machdep.c (working copy) @@ -344,9 +344,16 @@ return (4); } +struct cpu_group * +platform_smp_topo(void) +{ + return (smp_topo_none()); +} + void platform_init_ap(int cpuid) { + int ipi_int_mask, clock_int_mask; KASSERT(cpuid == 1, ("AP has an invalid cpu id %d", cpuid)); @@ -356,6 +363,13 @@ kseg0_map_coherent(); sb_intr_init(cpuid); + + /* + * Unmask the clock and ipi interrupts. + */ + clock_int_mask = hard_int_mask(5); + ipi_int_mask = hard_int_mask(platform_ipi_intrnum()); + set_intr_mask(ALL_INT_MASK & ~(ipi_int_mask | clock_int_mask)); } int Index: sys/mips/include/hwfunc.h =================================================================== --- sys/mips/include/hwfunc.h (revision 208183) +++ sys/mips/include/hwfunc.h (working copy) @@ -93,5 +93,11 @@ */ extern int platform_num_processors(void); +/* + * Return the topology of processors on this platform + */ +struct cpu_group * platform_smp_topo(void); + + #endif /* SMP */ #endif /* !_MACHINE_HWFUNC_H_ */ Index: sys/mips/rmi/xlr_machdep.c =================================================================== --- sys/mips/rmi/xlr_machdep.c (revision 208183) +++ sys/mips/rmi/xlr_machdep.c (working copy) @@ -535,6 +535,8 @@ /* Setup interrupts for secondary CPUs here */ stat = mips_rd_status(); stat |= MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT; + KASSERT((stat & MIPS_SR_INT_IE) == 0, + ("Interrupts enabled in %s!", __func__)); mips_wr_status(stat); xlr_unmask_hard_irq((void *)platform_ipi_intrnum()); @@ -570,4 +572,11 @@ { return fls(xlr_boot1_info.cpu_online_map); } + +struct cpu_group * +platform_smp_topo() +{ + return smp_topo_2level(CG_SHARE_L2, platform_num_processors()/4, + CG_SHARE_L1, 4, CG_FLAG_THREAD); +} #endif Index: sys/mips/mips/mpboot.S =================================================================== --- sys/mips/mips/mpboot.S (revision 208183) +++ sys/mips/mips/mpboot.S (working copy) @@ -76,10 +76,8 @@ PTR_LA gp, _C_LABEL(_gp) -#ifndef TARGET_XLR_XLS jal platform_init_ap move a0, s0 -#endif jal smp_init_secondary move a0, s0 Index: sys/mips/mips/mp_machdep.c =================================================================== --- sys/mips/mips/mp_machdep.c (revision 208183) +++ sys/mips/mips/mp_machdep.c (working copy) @@ -196,8 +196,7 @@ struct cpu_group * cpu_topo(void) { - - return (smp_topo_none()); + return platform_smp_topo(); } int @@ -238,10 +237,6 @@ void smp_init_secondary(u_int32_t cpuid) { -#ifndef TARGET_XLR_XLS - int ipi_int_mask, clock_int_mask; -#endif - /* TLB */ Mips_SetWIRED(0); Mips_TLBFlush(num_tlbentries); @@ -294,18 +289,7 @@ while (smp_started == 0) ; /* nothing */ -#ifndef TARGET_XLR_XLS /* - * Unmask the clock and ipi interrupts. - */ - clock_int_mask = hard_int_mask(5); - ipi_int_mask = hard_int_mask(platform_ipi_intrnum()); - set_intr_mask(ALL_INT_MASK & ~(ipi_int_mask | clock_int_mask)); -#else - platform_init_ap(cpuid); -#endif - - /* * Bootstrap the compare register. */ mips_wr_compare(mips_rd_count() + counter_freq / hz);
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