Date: Sun, 12 Sep 2010 16:50:53 +0530 From: "Jayachandran C." <c.jayachandran@gmail.com> To: freebsd-mips@freebsd.org Subject: patch - remove psracccess.S Message-ID: <AANLkTin1hSK6w2n7YhmS%2BWKXzyLYkDTivN7XHn%2B99nH2@mail.gmail.com>
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[-- Attachment #1 --]
The functions in sys/mips/mips/psraccess.S can be implemented with
mips_rd_status/mips_wr_status. Here's patch that does that. If there
are no objections, I will commit this some time tomorrow.
JC.
[-- Attachment #2 --]
Index: sys/conf/files.mips
===================================================================
--- sys/conf/files.mips (revision 212475)
+++ sys/conf/files.mips (working copy)
@@ -22,7 +22,6 @@
mips/mips/machdep.c standard
mips/mips/mp_machdep.c optional smp
mips/mips/mpboot.S optional smp
-mips/mips/psraccess.S standard
# ----------------------------------------------------------------------
# Phase 3
# ----------------------------------------------------------------------
Index: sys/mips/include/cpufunc.h
===================================================================
--- sys/mips/include/cpufunc.h (revision 212475)
+++ sys/mips/include/cpufunc.h (working copy)
@@ -266,6 +266,24 @@
}
}
+static __inline uint32_t
+set_intr_mask(uint32_t mask)
+{
+ uint32_t ostatus;
+
+ ostatus = mips_rd_status();
+ mask = (ostatus & ~MIPS_SR_INT_MASK) | (~mask & MIPS_SR_INT_MASK);
+ mips_wr_status(mask);
+ return (ostatus);
+}
+
+static __inline uint32_t
+get_intr_mask(void)
+{
+
+ return (mips_rd_status() & MIPS_SR_INT_MASK);
+}
+
static __inline void
breakpoint(void)
{
Index: sys/mips/include/md_var.h
===================================================================
--- sys/mips/include/md_var.h (revision 212475)
+++ sys/mips/include/md_var.h (working copy)
@@ -75,9 +75,5 @@
void platform_identify(void);
extern int busdma_swi_pending;
-void busdma_swi(void);
-
-u_int32_t set_intr_mask(u_int32_t);
-u_int32_t get_intr_mask(void);
-
+void busdma_swi(void);
#endif /* !_MACHINE_MD_VAR_H_ */
Index: sys/mips/mips/psraccess.S
===================================================================
--- sys/mips/mips/psraccess.S (revision 212475)
+++ sys/mips/mips/psraccess.S (working copy)
@@ -1,81 +0,0 @@
-/* $OpenBSD$ */
-/*
- * Copyright (c) 2001 Opsycon AB (www.opsycon.se / www.opsycon.com)
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
- * This product includes software developed by Opsycon AB, Sweden.
- * 4. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
- * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * JNPR: psraccess.S,v 1.4.2.1 2007/09/10 10:36:50 girish
- * $FreeBSD$
- *
- */
-
-/*
- * Low level code to manage processor specific registers.
- */
-
-#include <machine/asm.h>
-#include <machine/cpuregs.h>
-#include <machine/regnum.h>
-
-#include "opt_cputype.h"
-
-#include "assym.s"
-
-/*
- * FREEBSD_DEVELOPERS_FIXME
- * Some MIPS CPU may need delays using nops between executing CP0 Instructions
- */
-#define MIPS_CPU_NOP_DELAY nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;
-
- .set noreorder # Noreorder is default style!
-
-LEAF(set_intr_mask)
- li t0, MIPS_SR_INT_MASK # 1 means masked so invert.
- not a0, a0 # 1 means masked so invert.
- and a0, t0 # 1 means masked so invert.
- mfc0 v0, MIPS_COP_0_STATUS
- li v1, ~MIPS_SR_INT_MASK
- and v1, v0
- or v1, a0
- mtc0 v1, MIPS_COP_0_STATUS
- MIPS_CPU_NOP_DELAY
- move v0, v1
- jr ra
- nop
-
-END(set_intr_mask)
-
-LEAF(get_intr_mask)
- li a0, 0
- mfc0 v0, MIPS_COP_0_STATUS
- li v1, MIPS_SR_INT_MASK
- and v0, v1
- or v0, a0
- jr ra
- nop
-
-END(get_intr_mask)
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