Date: Fri, 15 Jul 2011 02:16:13 +0200 From: Robert Millan <rmh@debian.org> To: freebsd-mips@freebsd.org Subject: [PATCH] Fix initialization of i8259 controller on MALTA Message-ID: <CAOfDtXMgw%2BTa7=-uDz-O8xVFxAmQqREM7NMpAwgXMzr8mxbNeg@mail.gmail.com>
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[-- Attachment #1 --] Hi, i8259 controller is initialized incorrectly on MALTA. It writes mask bits to control register and control bits to mask register. The former causes ICW1_RESET|ICW1_LTIM combination to be written to control register, which on QEMU results in "level sensitive irq not supported" error. -- Robert Millan [-- Attachment #2 --] Fix initialization of i8259 controller. Opposite side is in qemu-0.14.1+dfsg/hw/i8259.c: pic_ioport_write() --- a/sys/mips/malta/gt_pci.c +++ b/sys/mips/malta/gt_pci.c @@ -326,15 +326,15 @@ ICW4_8086); /* mask all interrupts */ - bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1, sc->sc_imask & 0xff); /* enable special mask mode */ - bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0, OCW3_SEL | OCW3_ESMM | OCW3_SMM); /* read IRR by default */ - bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0, OCW3_SEL | OCW3_RR); /* reset, program device, 4 bytes */ @@ -348,15 +348,15 @@ ICW4_8086); /* mask all interrupts */ - bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1, sc->sc_imask & 0xff); /* enable special mask mode */ - bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0, OCW3_SEL | OCW3_ESMM | OCW3_SMM); /* read IRR by default */ - bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1, + bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0, OCW3_SEL | OCW3_RR); /*home | help
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