Date: Sun, 15 Sep 2013 18:55:45 GMT From: Robert Watson <rwatson@FreeBSD.org> To: Perforce Change Reviews <perforce@FreeBSD.org> Subject: PERFORCE change 717800 for review Message-ID: <201309151855.r8FItjSp050935@skunkworks.freebsd.org>
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http://p4web.freebsd.org/@@717800?ac=10 Change 717800 by rwatson@rwatson_zenith_cl_cam_ac_uk on 2013/09/15 18:54:47 Clean up a variety of aspects of CheriBSD support for CHERI's capability coprocessor in preparation for further exception- handling work: (1) In a more structured way, allocate exception-handling reserved capability registers for kernel use: CHERI_CR_CTEMP for KR1C -- C-language temporary use prior to compiling the kernel with CHERI-aware Clang; and CHERI_REG_SEC0 for KR2C -- temporary storage of a preempted $c0 prior to formal saving of the user thread context. (2) Now that KR2C is used for the saved $c0, start managing the previously occupied $c25 as part of the user context explicitly, effective returning it to general-purpose use by the compiler. This increases the size of the saved user thread context from 27 capability registers to 28. (3) Explicitly name $c24 and $c26 as RCC and IDC in various pieces of C and assembly code to make usage more clear. (4) Prefer #defines for various register names in kernel assembly -- e.g., CHERI_REG_KDC instead of $c30, which (on the whole) makes things more readable. (5) Use bzero rather than a series of inline capability preparations to initialise the majority of a user thread's CP2 context. (6) Improve comments and remove some XXXRW notes in a few places (and in one or two add them). (7) Print the complete set of CP2 registers in DDB rather than just most of them. Affected files ... .. //depot/projects/ctsrd/cheribsd/src/sys/mips/cheri/cheri.c#15 edit .. //depot/projects/ctsrd/cheribsd/src/sys/mips/include/cheri.h#21 edit .. //depot/projects/ctsrd/cheribsd/src/sys/mips/include/cheriasm.h#11 edit .. //depot/projects/ctsrd/cheribsd/src/sys/mips/include/cherireg.h#11 edit Differences ... ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/cheri/cheri.c#15 (text+ko) ==== @@ -1,5 +1,5 @@ /*- - * Copyright (c) 2011-2012 Robert N. M. Watson + * Copyright (c) 2011-2013 Robert N. M. Watson * All rights reserved. * * This software was developed by SRI International and the University of @@ -97,11 +97,11 @@ * temporary preserved during kernel execution to avoid this. */ s = intr_disable(); - CHERI_CINCBASE(CHERI_CR_KR1C, CHERI_CR_KDC, (register_t)basep); - CHERI_CSETLEN(CHERI_CR_KR1C, CHERI_CR_KR1C, (register_t)length); - CHERI_CANDPERM(CHERI_CR_KR1C, CHERI_CR_KR1C, (register_t)perms); - CHERI_CSETTYPE(CHERI_CR_KR1C, CHERI_CR_KR1C, (register_t)otypep); - CHERI_CSC(CHERI_CR_KR1C, CHERI_CR_KDC, (register_t)cp, 0); + CHERI_CINCBASE(CHERI_CR_CTEMP, CHERI_CR_KDC, (register_t)basep); + CHERI_CSETLEN(CHERI_CR_CTEMP, CHERI_CR_CTEMP, (register_t)length); + CHERI_CANDPERM(CHERI_CR_CTEMP, CHERI_CR_CTEMP, (register_t)perms); + CHERI_CSETTYPE(CHERI_CR_CTEMP, CHERI_CR_CTEMP, (register_t)otypep); + CHERI_CSC(CHERI_CR_CTEMP, CHERI_CR_KDC, (register_t)cp, 0); intr_restore(s); } @@ -169,8 +169,8 @@ * temporary preserved during kernel execution to avoid this. */ s = intr_disable(); - cheri_capability_load(CHERI_CR_KR1C, cp_from); - cheri_capability_store(CHERI_CR_KR1C, cp_to); + cheri_capability_load(CHERI_CR_CTEMP, cp_from); + cheri_capability_store(CHERI_CR_CTEMP, cp_to); intr_restore(s); } @@ -178,6 +178,7 @@ cheri_context_copy(struct cheri_frame *cf_destp, struct cheri_frame *cf_srcp) { + /* XXXRW: Use a capability-aware memcpy here instead. */ cheri_capability_copy(&cf_destp->cf_c0, &cf_srcp->cf_c0); cheri_capability_copy(&cf_destp->cf_c1, &cf_srcp->cf_c1); cheri_capability_copy(&cf_destp->cf_c2, &cf_srcp->cf_c2); @@ -202,12 +203,9 @@ cheri_capability_copy(&cf_destp->cf_c21, &cf_srcp->cf_c21); cheri_capability_copy(&cf_destp->cf_c22, &cf_srcp->cf_c22); cheri_capability_copy(&cf_destp->cf_c23, &cf_srcp->cf_c23); - cheri_capability_copy(&cf_destp->cf_c24, &cf_srcp->cf_c24); - cheri_capability_copy(&cf_destp->cf_c26, &cf_srcp->cf_c26); - /* - * XXXRW: not in CHERI ISAv2: - * cheri_capability_copy(&cf_destp->cf_tsc, &cf_srcp->cf_tsc); - */ + cheri_capability_copy(&cf_destp->cf_rcc, &cf_srcp->cf_rcc); + cheri_capability_copy(&cf_destp->cf_c25, &cf_srcp->cf_c25); + cheri_capability_copy(&cf_destp->cf_idc, &cf_srcp->cf_idc); cheri_capability_copy(&cf_destp->cf_pcc, &cf_srcp->cf_pcc); } @@ -223,36 +221,8 @@ * propagate around rights as required. */ cfp = &td->td_pcb->pcb_cheriframe; + bzero(cfp, sizeof(*cfp)); cheri_capability_set_user(&cfp->cf_c0); - cheri_capability_set_null(&cfp->cf_c1); - cheri_capability_set_null(&cfp->cf_c2); - cheri_capability_set_null(&cfp->cf_c3); - cheri_capability_set_null(&cfp->cf_c4); - cheri_capability_set_null(&cfp->cf_c5); - cheri_capability_set_null(&cfp->cf_c6); - cheri_capability_set_null(&cfp->cf_c7); - cheri_capability_set_null(&cfp->cf_c8); - cheri_capability_set_null(&cfp->cf_c9); - cheri_capability_set_null(&cfp->cf_c10); - cheri_capability_set_null(&cfp->cf_c11); - cheri_capability_set_null(&cfp->cf_c12); - cheri_capability_set_null(&cfp->cf_c13); - cheri_capability_set_null(&cfp->cf_c14); - cheri_capability_set_null(&cfp->cf_c15); - cheri_capability_set_null(&cfp->cf_c16); - cheri_capability_set_null(&cfp->cf_c17); - cheri_capability_set_null(&cfp->cf_c18); - cheri_capability_set_null(&cfp->cf_c19); - cheri_capability_set_null(&cfp->cf_c20); - cheri_capability_set_null(&cfp->cf_c21); - cheri_capability_set_null(&cfp->cf_c22); - cheri_capability_set_null(&cfp->cf_c23); - cheri_capability_set_null(&cfp->cf_c24); - cheri_capability_set_null(&cfp->cf_c26); - /* - * XXXRW: not in CHERI ISAv2: - * cheri_capability_set_null(&cfp->cf_tsc); - */ cheri_capability_set_user(&cfp->cf_pcc); } @@ -286,57 +256,57 @@ /* C0 */ intr_disable(); - CHERI_CLC(CHERI_CR_KR1C, CHERI_CR_KDC, &cheriframe->cf_c0, 0); - CHERI_GETCAPREG(CHERI_CR_KR1C, c); - CHERI_CGETTAG(ctag, CHERI_CR_KR1C); + CHERI_CLC(CHERI_CR_CTEMP, CHERI_CR_KDC, &cheriframe->cf_c0, 0); + CHERI_GETCAPREG(CHERI_CR_CTEMP, c); + CHERI_CGETTAG(ctag, CHERI_CR_CTEMP); intr_enable(); CHERI_REG_PRINT(c, ctag, 0); /* C1 */ intr_disable(); - CHERI_CLC(CHERI_CR_KR1C, CHERI_CR_KDC, &cheriframe->cf_c1, 0); - CHERI_GETCAPREG(CHERI_CR_KR1C, c); - CHERI_CGETTAG(ctag, CHERI_CR_KR1C); + CHERI_CLC(CHERI_CR_CTEMP, CHERI_CR_KDC, &cheriframe->cf_c1, 0); + CHERI_GETCAPREG(CHERI_CR_CTEMP, c); + CHERI_CGETTAG(ctag, CHERI_CR_CTEMP); intr_enable(); CHERI_REG_PRINT(c, ctag, 1); /* C2 */ intr_disable(); - CHERI_CLC(CHERI_CR_KR1C, CHERI_CR_KDC, &cheriframe->cf_c2, 0); - CHERI_GETCAPREG(CHERI_CR_KR1C, c); - CHERI_CGETTAG(ctag, CHERI_CR_KR1C); + CHERI_CLC(CHERI_CR_CTEMP, CHERI_CR_KDC, &cheriframe->cf_c2, 0); + CHERI_GETCAPREG(CHERI_CR_CTEMP, c); + CHERI_CGETTAG(ctag, CHERI_CR_CTEMP); intr_enable(); CHERI_REG_PRINT(c, ctag, 2); /* C3 */ intr_disable(); - CHERI_CLC(CHERI_CR_KR1C, CHERI_CR_KDC, &cheriframe->cf_c3, 0); - CHERI_GETCAPREG(CHERI_CR_KR1C, c); - CHERI_CGETTAG(ctag, CHERI_CR_KR1C); + CHERI_CLC(CHERI_CR_CTEMP, CHERI_CR_KDC, &cheriframe->cf_c3, 0); + CHERI_GETCAPREG(CHERI_CR_CTEMP, c); + CHERI_CGETTAG(ctag, CHERI_CR_CTEMP); intr_enable(); CHERI_REG_PRINT(c, ctag, 3); - /* C24 */ + /* C24 - RCC */ intr_disable(); - CHERI_CLC(CHERI_CR_KR1C, CHERI_CR_KDC, &cheriframe->cf_c24, 0); - CHERI_GETCAPREG(CHERI_CR_KR1C, c); - CHERI_CGETTAG(ctag, CHERI_CR_KR1C); + CHERI_CLC(CHERI_CR_CTEMP, CHERI_CR_KDC, &cheriframe->cf_rcc, 0); + CHERI_GETCAPREG(CHERI_CR_CTEMP, c); + CHERI_CGETTAG(ctag, CHERI_CR_CTEMP); intr_enable(); CHERI_REG_PRINT(c, ctag, 24); - /* C26 */ + /* C26 - IDC */ intr_disable(); - CHERI_CLC(CHERI_CR_KR1C, CHERI_CR_KDC, &cheriframe->cf_c26, 0); - CHERI_GETCAPREG(CHERI_CR_KR1C, c); - CHERI_CGETTAG(ctag, CHERI_CR_KR1C); + CHERI_CLC(CHERI_CR_CTEMP, CHERI_CR_KDC, &cheriframe->cf_idc, 0); + CHERI_GETCAPREG(CHERI_CR_CTEMP, c); + CHERI_CGETTAG(ctag, CHERI_CR_CTEMP); intr_enable(); CHERI_REG_PRINT(c, ctag, 26); - /* EPCC */ + /* C31 - saved PCC */ intr_disable(); - CHERI_CLC(CHERI_CR_KR1C, CHERI_CR_KDC, &cheriframe->cf_pcc, 0); - CHERI_GETCAPREG(CHERI_CR_KR1C, c); - CHERI_CGETTAG(ctag, CHERI_CR_KR1C); + CHERI_CLC(CHERI_CR_CTEMP, CHERI_CR_KDC, &cheriframe->cf_pcc, 0); + CHERI_GETCAPREG(CHERI_CR_CTEMP, c); + CHERI_CGETTAG(ctag, CHERI_CR_CTEMP); intr_enable(); CHERI_REG_PRINT(c, ctag, 31); @@ -377,9 +347,9 @@ * XXXRW: Possibly ECAPMODE should be EPROT or ESANDBOX? */ intr_disable(); - CHERI_CLC(CHERI_CR_KR1C, CHERI_CR_KDC, + CHERI_CLC(CHERI_CR_CTEMP, CHERI_CR_KDC, &td->td_pcb->pcb_cheriframe.cf_c0, 0); - CHERI_GETCAPREG(CHERI_CR_KR1C, c); + CHERI_GETCAPREG(CHERI_CR_CTEMP, c); intr_enable(); if (c.c_perms != CHERI_CAP_USER_PERMS || c.c_base != CHERI_CAP_USER_BASE || @@ -471,24 +441,19 @@ db_printf("Thread %d at %p\n", td->td_tid, td); db_printf("CHERI frame at %p\n", cfp); - /* Laboriously load and print each capability. */ - for (i = 0; i < 25; i++) { + /* Laboriously load and print each user capability. */ + for (i = 0; i < 27; i++) { s = intr_disable(); - cheri_capability_load(CHERI_CR_KR1C, + cheri_capability_load(CHERI_CR_CTEMP, (struct chericap *)&cfp->cf_c0 + i); - DB_CHERI_REG_PRINT_NUM(CHERI_CR_KR1C, i); + DB_CHERI_REG_PRINT_NUM(CHERI_CR_CTEMP, i); intr_restore(s); } db_printf("\nPCC:\n"); s = intr_disable(); -#if 0 - cheri_capability_load(CHERI_CR_KR1C, (struct chericap *)&cfp->cf_c0 + - CHERI_CR_TSC_OFF); - DB_CHERI_REG_PRINT_NUM(CHERI_CR_KR1C, CHERI_CR_TSC); -#endif - cheri_capability_load(CHERI_CR_KR1C, (struct chericap *)&cfp->cf_c0 + + cheri_capability_load(CHERI_CR_CTEMP, (struct chericap *)&cfp->cf_c0 + CHERI_CR_PCC_OFF); - DB_CHERI_REG_PRINT_NUM(CHERI_CR_KR1C, CHERI_CR_EPCC); + DB_CHERI_REG_PRINT_NUM(CHERI_CR_CTEMP, CHERI_CR_EPCC); intr_restore(s); } #endif ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/include/cheri.h#21 (text+ko) ==== @@ -41,7 +41,8 @@ #include <sys/types.h> /* - * Canonical C-language representation of a capability. + * Canonical C-language representation of a capability -- for compilers that + * don't support capabilities; for them, we'll provide __capability void *. */ #define CHERICAP_SIZE 32 struct chericap { @@ -77,17 +78,13 @@ /* * General-purpose capabilities -- note, numbering is from v1.7 of the * CHERI ISA spec (ISAv2). - * - * XXXRW: Currently, C25 is used in-kernel to maintain a saved UDC - * (C0), and so not part of cheri_frame. This will change in the - * future. */ struct chericap cf_c1, cf_c2, cf_c3, cf_c4; struct chericap cf_c5, cf_c6, cf_c7; struct chericap cf_c8, cf_c9, cf_c10, cf_c11, cf_c12; struct chericap cf_c13, cf_c14, cf_c15, cf_c16, cf_c17; struct chericap cf_c18, cf_c19, cf_c20, cf_c21, cf_c22; - struct chericap cf_c23, cf_c24, cf_c26; + struct chericap cf_c23, cf_rcc, cf_c25, cf_idc; /* * Special-purpose capability registers that must be preserved on a @@ -101,7 +98,7 @@ */ struct chericap cf_pcc; }; -CTASSERT(sizeof(struct cheri_frame) == (27 * CHERICAP_SIZE)); +CTASSERT(sizeof(struct cheri_frame) == (28 * CHERICAP_SIZE)); #endif /* ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/include/cheriasm.h#11 (text+ko) ==== @@ -1,5 +1,5 @@ /*- - * Copyright (c) 2012 Robert N. M. Watson + * Copyright (c) 2012-2013 Robert N. M. Watson * All rights reserved. * * This software was developed by SRI International and the University of @@ -36,6 +36,57 @@ #endif /* + * 27 user-context registers -- with names where appropriate. + */ +#define CHERI_REG_C0 $c0 /* MIPS legacy load/store capability. */ +#define CHERI_REG_C1 $c1 +#define CHERI_REG_C2 $c2 +#define CHERI_REG_C3 $c3 +#define CHERI_REG_C4 $c4 +#define CHERI_REG_C5 $c5 +#define CHERI_REG_C6 $c6 +#define CHERI_REG_C7 $c7 +#define CHERI_REG_C8 $c8 +#define CHERI_REG_C9 $c9 +#define CHERI_REG_C10 $c10 +#define CHERI_REG_C11 $c11 +#define CHERI_REG_C12 $c12 +#define CHERI_REG_C13 $c13 +#define CHERI_REG_C14 $c14 +#define CHERI_REG_C15 $c15 +#define CHERI_REG_C16 $c16 +#define CHERI_REG_C17 $c17 +#define CHERI_REG_C18 $c18 +#define CHERI_REG_C19 $c19 +#define CHERI_REG_C20 $c20 +#define CHERI_REG_C21 $c21 +#define CHERI_REG_C22 $c22 +#define CHERI_REG_C23 $c23 +#define CHERI_REG_RCC $c24 /* Return code capability. */ +#define CHERI_REG_C25 $c25 /* Notionally reserved for exception-use. */ +#define CHERI_REG_IDC $c26 /* Invoked data capability. */ + +/* 5 exception-context registers -- with names where appropriate. */ +#define CHERI_REG_KR1C $c27 /* Kernel exception handling capability (1). */ +#define CHERI_REG_KR2C $c28 /* Kernel exception handling capability (2). */ +#define CHERI_REG_KCC $c29 /* Kernel code capability. */ +#define CHERI_REG_KDC $c30 /* Kernel data capability. */ +#define CHERI_REG_EPCC $c31 /* Exception program counter capability. */ + +/* + * C-level code will manipulate capabilities using this exception-handling + * register; label it here for consistency. Interrupts must be disabled while + * using the register to prevent awkward preemptions. + */ +#define CHERI_REG_CTEMP CHERI_REG_KR1C /* C-level capability manipulation. */ + +/* + * Where to save the user $c0 during low-level exception handling. Possibly + * this should be an argument to macros rather than hard-coded in the macros. + */ +#define CHERI_REG_SEC0 CHERI_REG_KR2C /* Saved $c0 in exception handling. */ + +/* * Assembly code to be used in CHERI exception handling and context switching. * * When entering an exception handler from userspace, conditionally save the @@ -49,8 +100,9 @@ andi reg, reg, MIPS_SR_KSU_USER; \ beq reg, $0, 64f; \ nop; \ - cmove $c25, $c0; \ - cmove $c0, $c30; \ + /* Save user $c0; install kernel $c0. */ \ + cmove CHERI_REG_SEC0, CHERI_REG_C0; \ + cmove CHERI_REG_C0, CHERI_REG_KDC; \ 64: /* @@ -72,27 +124,29 @@ beq reg, $0, 65f; \ nop; \ b 66f; \ - cmove $c0, $c25; /* Branch-delay; install UDC in C0. */ \ + /* If returning to userspace, restore saved user $c0. */ \ + cmove CHERI_REG_C0, CHERI_REG_SEC0; /* Branch-delay. */ \ 65: \ - cmove $c31, $c29; /* Install kernel PCC in EPCC. */ \ + /* If returning to kernelspace, reinstall kernel code PCC. */ \ + cmove CHERI_REG_EPCC, CHERI_REG_KCC; \ 66: /* * Macros to save and restore CHERI capability registers registers from * pcb.pcb_cheriframe, individually and in quantity. Explicitly use $kdc * ($30), which U_PCB_CHERIFRAME is assumed to be valid for, but that the - * userspace $c0 has been set aside in $sc0 ($c25). This assumes previous or - * further calls to CHERI_EXECPTION_ENTER() and CHERI_EXCEPTION_RETURN() to + * userspace $c0 has been set aside in CHERI_REG_SEC0. This assumes previous + * or further calls to CHERI_EXECPTION_ENTER() and CHERI_EXCEPTION_RETURN() to * manage $c0. */ #define SZCAP 32 #define SAVE_U_PCB_CHERIREG(creg, offs, base, treg) \ PTR_ADDIU treg, base, U_PCB_CHERIFRAME; \ - csc creg, treg, (SZCAP * offs)($c30) + csc creg, treg, (SZCAP * offs)(CHERI_REG_KDC) #define RESTORE_U_PCB_CHERIREG(creg, offs, base, treg) \ PTR_ADDIU treg, base, U_PCB_CHERIFRAME; \ - clc creg, treg, (SZCAP * offs)($c30) + clc creg, treg, (SZCAP * offs)(CHERI_REG_KDC) /* * XXXRW: Update once the assembler supports reserved CHERI register names to @@ -105,61 +159,63 @@ * XXXRW: Note hard-coding of UDC here. */ #define SAVE_CHERI_CONTEXT(base, treg) \ - SAVE_U_PCB_CHERIREG($c25, CHERI_CR_C0_OFF, base, treg); \ - SAVE_U_PCB_CHERIREG($c1, CHERI_CR_C1_OFF, base, treg); \ - SAVE_U_PCB_CHERIREG($c2, CHERI_CR_C2_OFF, base, treg); \ - SAVE_U_PCB_CHERIREG($c3, CHERI_CR_C3_OFF, base, treg); \ - SAVE_U_PCB_CHERIREG($c4, CHERI_CR_C4_OFF, base, treg); \ - SAVE_U_PCB_CHERIREG($c5, CHERI_CR_C5_OFF, base, treg); \ - SAVE_U_PCB_CHERIREG($c6, CHERI_CR_C6_OFF, base, treg); \ - SAVE_U_PCB_CHERIREG($c7, CHERI_CR_C7_OFF, base, treg); \ - SAVE_U_PCB_CHERIREG($c8, CHERI_CR_C8_OFF, base, treg); \ - SAVE_U_PCB_CHERIREG($c9, CHERI_CR_C9_OFF, base, treg); \ - SAVE_U_PCB_CHERIREG($c10, CHERI_CR_C10_OFF, base, treg); \ - SAVE_U_PCB_CHERIREG($c11, CHERI_CR_C11_OFF, base, treg); \ - SAVE_U_PCB_CHERIREG($c12, CHERI_CR_C12_OFF, base, treg); \ - SAVE_U_PCB_CHERIREG($c13, CHERI_CR_C13_OFF, base, treg); \ - SAVE_U_PCB_CHERIREG($c14, CHERI_CR_C14_OFF, base, treg); \ - SAVE_U_PCB_CHERIREG($c15, CHERI_CR_C15_OFF, base, treg); \ - SAVE_U_PCB_CHERIREG($c16, CHERI_CR_C16_OFF, base, treg); \ - SAVE_U_PCB_CHERIREG($c17, CHERI_CR_C17_OFF, base, treg); \ - SAVE_U_PCB_CHERIREG($c18, CHERI_CR_C18_OFF, base, treg); \ - SAVE_U_PCB_CHERIREG($c19, CHERI_CR_C19_OFF, base, treg); \ - SAVE_U_PCB_CHERIREG($c20, CHERI_CR_C20_OFF, base, treg); \ - SAVE_U_PCB_CHERIREG($c21, CHERI_CR_C21_OFF, base, treg); \ - SAVE_U_PCB_CHERIREG($c22, CHERI_CR_C22_OFF, base, treg); \ - SAVE_U_PCB_CHERIREG($c23, CHERI_CR_C23_OFF, base, treg); \ - SAVE_U_PCB_CHERIREG($c24, CHERI_CR_C24_OFF, base, treg); \ - SAVE_U_PCB_CHERIREG($c26, CHERI_CR_C26_OFF, base, treg); \ - SAVE_U_PCB_CHERIREG($c31, CHERI_CR_PCC_OFF, base, treg) + SAVE_U_PCB_CHERIREG(CHERI_REG_SEC0, CHERI_CR_C0_OFF, base, treg); \ + SAVE_U_PCB_CHERIREG(CHERI_REG_C1, CHERI_CR_C1_OFF, base, treg); \ + SAVE_U_PCB_CHERIREG(CHERI_REG_C2, CHERI_CR_C2_OFF, base, treg); \ + SAVE_U_PCB_CHERIREG(CHERI_REG_C3, CHERI_CR_C3_OFF, base, treg); \ + SAVE_U_PCB_CHERIREG(CHERI_REG_C4, CHERI_CR_C4_OFF, base, treg); \ + SAVE_U_PCB_CHERIREG(CHERI_REG_C5, CHERI_CR_C5_OFF, base, treg); \ + SAVE_U_PCB_CHERIREG(CHERI_REG_C6, CHERI_CR_C6_OFF, base, treg); \ + SAVE_U_PCB_CHERIREG(CHERI_REG_C7, CHERI_CR_C7_OFF, base, treg); \ + SAVE_U_PCB_CHERIREG(CHERI_REG_C8, CHERI_CR_C8_OFF, base, treg); \ + SAVE_U_PCB_CHERIREG(CHERI_REG_C9, CHERI_CR_C9_OFF, base, treg); \ + SAVE_U_PCB_CHERIREG(CHERI_REG_C10, CHERI_CR_C10_OFF, base, treg); \ + SAVE_U_PCB_CHERIREG(CHERI_REG_C11, CHERI_CR_C11_OFF, base, treg); \ + SAVE_U_PCB_CHERIREG(CHERI_REG_C12, CHERI_CR_C12_OFF, base, treg); \ + SAVE_U_PCB_CHERIREG(CHERI_REG_C13, CHERI_CR_C13_OFF, base, treg); \ + SAVE_U_PCB_CHERIREG(CHERI_REG_C14, CHERI_CR_C14_OFF, base, treg); \ + SAVE_U_PCB_CHERIREG(CHERI_REG_C15, CHERI_CR_C15_OFF, base, treg); \ + SAVE_U_PCB_CHERIREG(CHERI_REG_C16, CHERI_CR_C16_OFF, base, treg); \ + SAVE_U_PCB_CHERIREG(CHERI_REG_C17, CHERI_CR_C17_OFF, base, treg); \ + SAVE_U_PCB_CHERIREG(CHERI_REG_C18, CHERI_CR_C18_OFF, base, treg); \ + SAVE_U_PCB_CHERIREG(CHERI_REG_C19, CHERI_CR_C19_OFF, base, treg); \ + SAVE_U_PCB_CHERIREG(CHERI_REG_C20, CHERI_CR_C20_OFF, base, treg); \ + SAVE_U_PCB_CHERIREG(CHERI_REG_C21, CHERI_CR_C21_OFF, base, treg); \ + SAVE_U_PCB_CHERIREG(CHERI_REG_C22, CHERI_CR_C22_OFF, base, treg); \ + SAVE_U_PCB_CHERIREG(CHERI_REG_C23, CHERI_CR_C23_OFF, base, treg); \ + SAVE_U_PCB_CHERIREG(CHERI_REG_RCC, CHERI_CR_RCC_OFF, base, treg); \ + SAVE_U_PCB_CHERIREG(CHERI_REG_C25, CHERI_CR_C25_OFF, base, treg); \ + SAVE_U_PCB_CHERIREG(CHERI_REG_IDC, CHERI_CR_IDC_OFF, base, treg); \ + SAVE_U_PCB_CHERIREG(CHERI_REG_EPCC, CHERI_CR_PCC_OFF, base, treg) #define RESTORE_CHERI_CONTEXT(base, treg) \ - RESTORE_U_PCB_CHERIREG($c25, CHERI_CR_C0_OFF, base, treg); \ - RESTORE_U_PCB_CHERIREG($c1, CHERI_CR_C1_OFF, base, treg); \ - RESTORE_U_PCB_CHERIREG($c2, CHERI_CR_C2_OFF, base, treg); \ - RESTORE_U_PCB_CHERIREG($c3, CHERI_CR_C3_OFF, base, treg); \ - RESTORE_U_PCB_CHERIREG($c4, CHERI_CR_C4_OFF, base, treg); \ - RESTORE_U_PCB_CHERIREG($c5, CHERI_CR_C5_OFF, base, treg); \ - RESTORE_U_PCB_CHERIREG($c6, CHERI_CR_C6_OFF, base, treg); \ - RESTORE_U_PCB_CHERIREG($c7, CHERI_CR_C7_OFF, base, treg); \ - RESTORE_U_PCB_CHERIREG($c8, CHERI_CR_C8_OFF, base, treg); \ - RESTORE_U_PCB_CHERIREG($c9, CHERI_CR_C9_OFF, base, treg); \ - RESTORE_U_PCB_CHERIREG($c10, CHERI_CR_C10_OFF, base, treg); \ - RESTORE_U_PCB_CHERIREG($c11, CHERI_CR_C11_OFF, base, treg); \ - RESTORE_U_PCB_CHERIREG($c12, CHERI_CR_C12_OFF, base, treg); \ - RESTORE_U_PCB_CHERIREG($c13, CHERI_CR_C13_OFF, base, treg); \ - RESTORE_U_PCB_CHERIREG($c14, CHERI_CR_C14_OFF, base, treg); \ - RESTORE_U_PCB_CHERIREG($c15, CHERI_CR_C15_OFF, base, treg); \ - RESTORE_U_PCB_CHERIREG($c16, CHERI_CR_C16_OFF, base, treg); \ - RESTORE_U_PCB_CHERIREG($c17, CHERI_CR_C17_OFF, base, treg); \ - RESTORE_U_PCB_CHERIREG($c18, CHERI_CR_C18_OFF, base, treg); \ - RESTORE_U_PCB_CHERIREG($c19, CHERI_CR_C19_OFF, base, treg); \ - RESTORE_U_PCB_CHERIREG($c20, CHERI_CR_C20_OFF, base, treg); \ - RESTORE_U_PCB_CHERIREG($c21, CHERI_CR_C21_OFF, base, treg); \ - RESTORE_U_PCB_CHERIREG($c22, CHERI_CR_C22_OFF, base, treg); \ - RESTORE_U_PCB_CHERIREG($c23, CHERI_CR_C23_OFF, base, treg); \ - RESTORE_U_PCB_CHERIREG($c24, CHERI_CR_C24_OFF, base, treg); \ - RESTORE_U_PCB_CHERIREG($c26, CHERI_CR_C26_OFF, base, treg); \ - RESTORE_U_PCB_CHERIREG($c31, CHERI_CR_PCC_OFF, base, treg) + RESTORE_U_PCB_CHERIREG(CHERI_REG_SEC0, CHERI_CR_C0_OFF, base, treg); \ + RESTORE_U_PCB_CHERIREG(CHERI_REG_C1, CHERI_CR_C1_OFF, base, treg); \ + RESTORE_U_PCB_CHERIREG(CHERI_REG_C2, CHERI_CR_C2_OFF, base, treg); \ + RESTORE_U_PCB_CHERIREG(CHERI_REG_C3, CHERI_CR_C3_OFF, base, treg); \ + RESTORE_U_PCB_CHERIREG(CHERI_REG_C4, CHERI_CR_C4_OFF, base, treg); \ + RESTORE_U_PCB_CHERIREG(CHERI_REG_C5, CHERI_CR_C5_OFF, base, treg); \ + RESTORE_U_PCB_CHERIREG(CHERI_REG_C6, CHERI_CR_C6_OFF, base, treg); \ + RESTORE_U_PCB_CHERIREG(CHERI_REG_C7, CHERI_CR_C7_OFF, base, treg); \ + RESTORE_U_PCB_CHERIREG(CHERI_REG_C8, CHERI_CR_C8_OFF, base, treg); \ + RESTORE_U_PCB_CHERIREG(CHERI_REG_C9, CHERI_CR_C9_OFF, base, treg); \ + RESTORE_U_PCB_CHERIREG(CHERI_REG_C10, CHERI_CR_C10_OFF, base, treg); \ + RESTORE_U_PCB_CHERIREG(CHERI_REG_C11, CHERI_CR_C11_OFF, base, treg); \ + RESTORE_U_PCB_CHERIREG(CHERI_REG_C12, CHERI_CR_C12_OFF, base, treg); \ + RESTORE_U_PCB_CHERIREG(CHERI_REG_C13, CHERI_CR_C13_OFF, base, treg); \ + RESTORE_U_PCB_CHERIREG(CHERI_REG_C14, CHERI_CR_C14_OFF, base, treg); \ + RESTORE_U_PCB_CHERIREG(CHERI_REG_C15, CHERI_CR_C15_OFF, base, treg); \ + RESTORE_U_PCB_CHERIREG(CHERI_REG_C16, CHERI_CR_C16_OFF, base, treg); \ + RESTORE_U_PCB_CHERIREG(CHERI_REG_C17, CHERI_CR_C17_OFF, base, treg); \ + RESTORE_U_PCB_CHERIREG(CHERI_REG_C18, CHERI_CR_C18_OFF, base, treg); \ + RESTORE_U_PCB_CHERIREG(CHERI_REG_C19, CHERI_CR_C19_OFF, base, treg); \ + RESTORE_U_PCB_CHERIREG(CHERI_REG_C20, CHERI_CR_C20_OFF, base, treg); \ + RESTORE_U_PCB_CHERIREG(CHERI_REG_C21, CHERI_CR_C21_OFF, base, treg); \ + RESTORE_U_PCB_CHERIREG(CHERI_REG_C22, CHERI_CR_C22_OFF, base, treg); \ + RESTORE_U_PCB_CHERIREG(CHERI_REG_C23, CHERI_CR_C23_OFF, base, treg); \ + RESTORE_U_PCB_CHERIREG(CHERI_REG_RCC, CHERI_CR_RCC_OFF, base, treg); \ + RESTORE_U_PCB_CHERIREG(CHERI_REG_C25, CHERI_CR_C25_OFF, base, treg); \ + RESTORE_U_PCB_CHERIREG(CHERI_REG_IDC, CHERI_CR_IDC_OFF, base, treg); \ + RESTORE_U_PCB_CHERIREG(CHERI_REG_EPCC, CHERI_CR_PCC_OFF, base, treg) #endif /* _MIPS_INCLUDE_CHERIASM_H_ */ ==== //depot/projects/ctsrd/cheribsd/src/sys/mips/include/cherireg.h#11 (text+ko) ==== @@ -127,29 +127,17 @@ #define CHERI_CR_C21 21 #define CHERI_CR_C22 22 #define CHERI_CR_C23 23 -#define CHERI_CR_C24 24 +#define CHERI_CR_RCC 24 #define CHERI_CR_C25 25 -#define CHERI_CR_C26 26 -#define CHERI_CR_C27 27 -#define CHERI_CR_C28 28 -#define CHERI_CR_C29 29 -#define CHERI_CR_C30 30 -#define CHERI_CR_C31 31 +#define CHERI_CR_IDC 26 +#define CHERI_CR_KR1C 27 +#define CHERI_CR_KR2C 28 +#define CHERI_CR_KCC 29 +#define CHERI_CR_KDC 30 +#define CHERI_CR_EPCC 31 -/* - * XXXRW: Note that UDC is used by the kernel to hold the saved user data - * capability during kernel execution. In the future, this will change -- - * instead we will swap with KR2C, and save it to a frame to be used as needed - * later. In the mean time, userspace agrees not to use C25. - */ -#define CHERI_CR_RCC CHERI_CR_C24 /* Return code capability. */ -#define CHERI_CR_UDC CHERI_CR_C25 /* User data capability. */ -#define CHERI_CR_IDC CHERI_CR_C26 /* Invoked data capability.*/ -#define CHERI_CR_KR1C CHERI_CR_C27 /* Kernel reserved capability 1. */ -#define CHERI_CR_KR2C CHERI_CR_C28 /* Kernel reserved capability 2. */ -#define CHERI_CR_KCC CHERI_CR_C29 /* Kernel code capability. */ -#define CHERI_CR_KDC CHERI_CR_C30 /* Kernel data capability. */ -#define CHERI_CR_EPCC CHERI_CR_C31 /* Exception program counter cap. */ +#define CHERI_CR_CTEMP CHERI_CR_KR1C /* C-language temporary. */ +#define CHERI_CR_SEC0 CHERI_CR_KR2C /* Saved $c0 in exception handler. */ /* * Offsets of registers in struct cheri_frame -- must match the definition in @@ -179,9 +167,10 @@ #define CHERI_CR_C21_OFF 21 #define CHERI_CR_C22_OFF 22 #define CHERI_CR_C23_OFF 23 -#define CHERI_CR_C24_OFF 24 -#define CHERI_CR_C26_OFF 25 -#define CHERI_CR_PCC_OFF 26 +#define CHERI_CR_RCC_OFF 24 +#define CHERI_CR_C25_OFF 25 +#define CHERI_CR_IDC_OFF 26 +#define CHERI_CR_PCC_OFF 27 /* NB: Not register $c27! */ /* * List of CHERI capability cause code constants, which are used to
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