Date: Wed, 28 Nov 2018 06:54:14 +0000 (UTC) From: Andrew Rybchenko <arybchik@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r341108 - head/sys/dev/sfxge/common Message-ID: <201811280654.wAS6sEfd083933@repo.freebsd.org>
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Author: arybchik Date: Wed Nov 28 06:54:13 2018 New Revision: 341108 URL: https://svnweb.freebsd.org/changeset/base/341108 Log: sfxge(4): move port config to ef10 NIC board config Submitted by: Andy Moreton <amoreton at solarflare.com> Sponsored by: Solarflare Communications, Inc. Differential Revision: https://reviews.freebsd.org/D18184 Modified: head/sys/dev/sfxge/common/ef10_impl.h head/sys/dev/sfxge/common/ef10_nic.c head/sys/dev/sfxge/common/hunt_nic.c head/sys/dev/sfxge/common/medford2_nic.c (contents, props changed) head/sys/dev/sfxge/common/medford_nic.c Modified: head/sys/dev/sfxge/common/ef10_impl.h ============================================================================== --- head/sys/dev/sfxge/common/ef10_impl.h Wed Nov 28 06:54:02 2018 (r341107) +++ head/sys/dev/sfxge/common/ef10_impl.h Wed Nov 28 06:54:13 2018 (r341108) @@ -1201,11 +1201,6 @@ ef10_get_privilege_mask( __in efx_nic_t *enp, __out uint32_t *maskp); -extern __checkReturn efx_rc_t -ef10_external_port_mapping( - __in efx_nic_t *enp, - __in uint32_t port, - __out uint8_t *external_portp); #if EFSYS_OPT_RX_PACKED_STREAM Modified: head/sys/dev/sfxge/common/ef10_nic.c ============================================================================== --- head/sys/dev/sfxge/common/ef10_nic.c Wed Nov 28 06:54:02 2018 (r341107) +++ head/sys/dev/sfxge/common/ef10_nic.c Wed Nov 28 06:54:13 2018 (r341108) @@ -1494,7 +1494,7 @@ static struct ef10_external_port_map_s { }, }; - __checkReturn efx_rc_t +static __checkReturn efx_rc_t ef10_external_port_mapping( __in efx_nic_t *enp, __in uint32_t port, @@ -1573,14 +1573,33 @@ ef10_nic_board_cfg( __in efx_nic_t *enp) { const efx_nic_ops_t *enop = enp->en_enop; + efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); + efx_nic_cfg_t *encp = &(enp->en_nic_cfg); + uint32_t port; efx_rc_t rc; + /* Get the (zero-based) MCDI port number */ + if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0) + goto fail1; + + /* EFX MCDI interface uses one-based port numbers */ + emip->emi_port = port + 1; + + if ((rc = ef10_external_port_mapping(enp, port, + &encp->enc_external_port)) != 0) + goto fail2; + + /* Get remaining controller-specific board config */ if ((rc = enop->eno_board_cfg(enp)) != 0) if (rc != EACCES) - goto fail1; + goto fail3; return (0); +fail3: + EFSYS_PROBE(fail3); +fail2: + EFSYS_PROBE(fail2); fail1: EFSYS_PROBE1(fail1, efx_rc_t, rc); Modified: head/sys/dev/sfxge/common/hunt_nic.c ============================================================================== --- head/sys/dev/sfxge/common/hunt_nic.c Wed Nov 28 06:54:02 2018 (r341107) +++ head/sys/dev/sfxge/common/hunt_nic.c Wed Nov 28 06:54:13 2018 (r341108) @@ -103,13 +103,11 @@ fail1: hunt_board_cfg( __in efx_nic_t *enp) { - efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); efx_nic_cfg_t *encp = &(enp->en_nic_cfg); uint8_t mac_addr[6] = { 0 }; uint32_t board_type = 0; ef10_link_state_t els; efx_port_t *epp = &(enp->en_port); - uint32_t port; uint32_t pf; uint32_t vf; uint32_t mask; @@ -129,28 +127,14 @@ hunt_board_cfg( EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K == 8192); encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K; - - if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0) - goto fail1; - /* - * NOTE: The MCDI protocol numbers ports from zero. - * The common code MCDI interface numbers ports from one. - */ - emip->emi_port = port + 1; - - if ((rc = ef10_external_port_mapping(enp, port, - &encp->enc_external_port)) != 0) - goto fail2; - - /* * Get PCIe function number from firmware (used for * per-function privilege and dynamic config info). * - PCIe PF: pf = PF number, vf = 0xffff. * - PCIe VF: pf = parent PF, vf = VF number. */ if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0) - goto fail3; + goto fail1; encp->enc_pf = pf; encp->enc_vf = vf; @@ -171,7 +155,7 @@ hunt_board_cfg( rc = efx_mcdi_get_mac_address_vf(enp, mac_addr); } if (rc != 0) - goto fail4; + goto fail2; EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr); @@ -182,7 +166,7 @@ hunt_board_cfg( if (rc == EACCES) board_type = 0; else - goto fail5; + goto fail3; } encp->enc_board_type = board_type; @@ -190,11 +174,11 @@ hunt_board_cfg( /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */ if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0) - goto fail6; + goto fail4; /* Obtain the default PHY advertised capabilities */ if ((rc = ef10_phy_get_link(enp, &els)) != 0) - goto fail7; + goto fail5; epp->ep_default_adv_cap_mask = els.els_adv_cap_mask; epp->ep_adv_cap_mask = els.els_adv_cap_mask; @@ -225,7 +209,7 @@ hunt_board_cfg( else if ((rc == ENOTSUP) || (rc == ENOENT)) encp->enc_bug35388_workaround = B_FALSE; else - goto fail8; + goto fail6; /* * If the bug41750 workaround is enabled, then do not test interrupts, @@ -244,7 +228,7 @@ hunt_board_cfg( } else if ((rc == ENOTSUP) || (rc == ENOENT)) { encp->enc_bug41750_workaround = B_FALSE; } else { - goto fail9; + goto fail7; } if (EFX_PCI_FUNCTION_IS_VF(encp)) { /* Interrupt testing does not work for VFs. See bug50084. */ @@ -282,12 +266,12 @@ hunt_board_cfg( } else if ((rc == ENOTSUP) || (rc == ENOENT)) { encp->enc_bug26807_workaround = B_FALSE; } else { - goto fail10; + goto fail8; } /* Get clock frequencies (in MHz). */ if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0) - goto fail11; + goto fail9; /* * The Huntington timer quantum is 1536 sysclk cycles, documented for @@ -306,7 +290,7 @@ hunt_board_cfg( /* Check capabilities of running datapath firmware */ if ((rc = ef10_get_datapath_caps(enp)) != 0) - goto fail12; + goto fail10; /* Alignment for receive packet DMA buffers */ encp->enc_rx_buf_align_start = 1; @@ -356,13 +340,13 @@ hunt_board_cfg( * can result in time-of-check/time-of-use bugs. */ if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0) - goto fail13; + goto fail11; encp->enc_privilege_mask = mask; /* Get interrupt vector limits */ if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) { if (EFX_PCI_FUNCTION_IS_PF(encp)) - goto fail14; + goto fail12; /* Ignore error (cannot query vector limits from a VF). */ base = 0; @@ -378,7 +362,7 @@ hunt_board_cfg( encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT; if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0) - goto fail15; + goto fail13; encp->enc_required_pcie_bandwidth_mbps = bandwidth; /* All Huntington devices have a PCIe Gen3, 8 lane connector */ @@ -386,10 +370,6 @@ hunt_board_cfg( return (0); -fail15: - EFSYS_PROBE(fail15); -fail14: - EFSYS_PROBE(fail14); fail13: EFSYS_PROBE(fail13); fail12: Modified: head/sys/dev/sfxge/common/medford2_nic.c ============================================================================== --- head/sys/dev/sfxge/common/medford2_nic.c Wed Nov 28 06:54:02 2018 (r341107) +++ head/sys/dev/sfxge/common/medford2_nic.c Wed Nov 28 06:54:13 2018 (r341108) @@ -77,13 +77,11 @@ fail1: medford2_board_cfg( __in efx_nic_t *enp) { - efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); efx_nic_cfg_t *encp = &(enp->en_nic_cfg); uint8_t mac_addr[6] = { 0 }; uint32_t board_type = 0; ef10_link_state_t els; efx_port_t *epp = &(enp->en_port); - uint32_t port; uint32_t pf; uint32_t vf; uint32_t mask; @@ -107,27 +105,14 @@ medford2_board_cfg( encp->enc_vi_window_shift = vi_window_shift; - if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0) - goto fail1; - /* - * NOTE: The MCDI protocol numbers ports from zero. - * The common code MCDI interface numbers ports from one. - */ - emip->emi_port = port + 1; - - if ((rc = ef10_external_port_mapping(enp, port, - &encp->enc_external_port)) != 0) - goto fail2; - - /* * Get PCIe function number from firmware (used for * per-function privilege and dynamic config info). * - PCIe PF: pf = PF number, vf = 0xffff. * - PCIe VF: pf = parent PF, vf = VF number. */ if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0) - goto fail3; + goto fail2; encp->enc_pf = pf; encp->enc_vf = vf; @@ -156,7 +141,7 @@ medford2_board_cfg( rc = efx_mcdi_get_mac_address_vf(enp, mac_addr); } if (rc != 0) - goto fail4; + goto fail3; EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr); @@ -167,7 +152,7 @@ medford2_board_cfg( if (rc == EACCES) board_type = 0; else - goto fail5; + goto fail4; } encp->enc_board_type = board_type; @@ -175,11 +160,11 @@ medford2_board_cfg( /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */ if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0) - goto fail6; + goto fail5; /* Obtain the default PHY advertised capabilities */ if ((rc = ef10_phy_get_link(enp, &els)) != 0) - goto fail7; + goto fail6; epp->ep_default_adv_cap_mask = els.els_adv_cap_mask; epp->ep_adv_cap_mask = els.els_adv_cap_mask; @@ -223,11 +208,11 @@ medford2_board_cfg( else if ((rc == ENOTSUP) || (rc == ENOENT)) encp->enc_bug61265_workaround = B_FALSE; else - goto fail8; + goto fail7; /* Get clock frequencies (in MHz). */ if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0) - goto fail9; + goto fail8; /* * The Medford2 timer quantum is 1536 dpcpu_clk cycles, documented for @@ -239,7 +224,7 @@ medford2_board_cfg( /* Check capabilities of running datapath firmware */ if ((rc = ef10_get_datapath_caps(enp)) != 0) - goto fail10; + goto fail9; /* Alignment for receive packet DMA buffers */ encp->enc_rx_buf_align_start = 1; @@ -247,7 +232,7 @@ medford2_board_cfg( /* Get the RX DMA end padding alignment configuration */ if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) { if (rc != EACCES) - goto fail11; + goto fail10; /* Assume largest tail padding size supported by hardware */ end_padding = 256; @@ -299,13 +284,13 @@ medford2_board_cfg( * can result in time-of-check/time-of-use bugs. */ if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0) - goto fail12; + goto fail11; encp->enc_privilege_mask = mask; /* Get interrupt vector limits */ if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) { if (EFX_PCI_FUNCTION_IS_PF(encp)) - goto fail13; + goto fail12; /* Ignore error (cannot query vector limits from a VF). */ base = 0; @@ -328,14 +313,12 @@ medford2_board_cfg( rc = medford2_nic_get_required_pcie_bandwidth(enp, &bandwidth); if (rc != 0) - goto fail14; + goto fail13; encp->enc_required_pcie_bandwidth_mbps = bandwidth; encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3; return (0); -fail14: - EFSYS_PROBE(fail14); fail13: EFSYS_PROBE(fail13); fail12: Modified: head/sys/dev/sfxge/common/medford_nic.c ============================================================================== --- head/sys/dev/sfxge/common/medford_nic.c Wed Nov 28 06:54:02 2018 (r341107) +++ head/sys/dev/sfxge/common/medford_nic.c Wed Nov 28 06:54:13 2018 (r341108) @@ -73,13 +73,11 @@ fail1: medford_board_cfg( __in efx_nic_t *enp) { - efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); efx_nic_cfg_t *encp = &(enp->en_nic_cfg); uint8_t mac_addr[6] = { 0 }; uint32_t board_type = 0; ef10_link_state_t els; efx_port_t *epp = &(enp->en_port); - uint32_t port; uint32_t pf; uint32_t vf; uint32_t mask; @@ -104,28 +102,14 @@ medford_board_cfg( EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K == 8192); encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K; - - if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0) - goto fail1; - /* - * NOTE: The MCDI protocol numbers ports from zero. - * The common code MCDI interface numbers ports from one. - */ - emip->emi_port = port + 1; - - if ((rc = ef10_external_port_mapping(enp, port, - &encp->enc_external_port)) != 0) - goto fail2; - - /* * Get PCIe function number from firmware (used for * per-function privilege and dynamic config info). * - PCIe PF: pf = PF number, vf = 0xffff. * - PCIe VF: pf = parent PF, vf = VF number. */ if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0) - goto fail3; + goto fail1; encp->enc_pf = pf; encp->enc_vf = vf; @@ -154,7 +138,7 @@ medford_board_cfg( rc = efx_mcdi_get_mac_address_vf(enp, mac_addr); } if (rc != 0) - goto fail4; + goto fail2; EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr); @@ -165,7 +149,7 @@ medford_board_cfg( if (rc == EACCES) board_type = 0; else - goto fail5; + goto fail3; } encp->enc_board_type = board_type; @@ -173,11 +157,11 @@ medford_board_cfg( /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */ if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0) - goto fail6; + goto fail4; /* Obtain the default PHY advertised capabilities */ if ((rc = ef10_phy_get_link(enp, &els)) != 0) - goto fail7; + goto fail5; epp->ep_default_adv_cap_mask = els.els_adv_cap_mask; epp->ep_adv_cap_mask = els.els_adv_cap_mask; @@ -221,11 +205,11 @@ medford_board_cfg( else if ((rc == ENOTSUP) || (rc == ENOENT)) encp->enc_bug61265_workaround = B_FALSE; else - goto fail8; + goto fail6; /* Get clock frequencies (in MHz). */ if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0) - goto fail9; + goto fail7; /* * The Medford timer quantum is 1536 dpcpu_clk cycles, documented for @@ -237,7 +221,7 @@ medford_board_cfg( /* Check capabilities of running datapath firmware */ if ((rc = ef10_get_datapath_caps(enp)) != 0) - goto fail10; + goto fail8; /* Alignment for receive packet DMA buffers */ encp->enc_rx_buf_align_start = 1; @@ -245,7 +229,7 @@ medford_board_cfg( /* Get the RX DMA end padding alignment configuration */ if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) { if (rc != EACCES) - goto fail11; + goto fail9; /* Assume largest tail padding size supported by hardware */ end_padding = 256; @@ -297,13 +281,13 @@ medford_board_cfg( * can result in time-of-check/time-of-use bugs. */ if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0) - goto fail12; + goto fail10; encp->enc_privilege_mask = mask; /* Get interrupt vector limits */ if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) { if (EFX_PCI_FUNCTION_IS_PF(encp)) - goto fail13; + goto fail11; /* Ignore error (cannot query vector limits from a VF). */ base = 0; @@ -326,16 +310,12 @@ medford_board_cfg( rc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth); if (rc != 0) - goto fail14; + goto fail12; encp->enc_required_pcie_bandwidth_mbps = bandwidth; encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3; return (0); -fail14: - EFSYS_PROBE(fail14); -fail13: - EFSYS_PROBE(fail13); fail12: EFSYS_PROBE(fail12); fail11:
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