Date: Wed, 20 Feb 2008 18:31:34 GMT From: "Randall R. Stewart" <rrs@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 135815 for review Message-ID: <200802201831.m1KIVYSr081473@repoman.freebsd.org>
next in thread | raw e-mail | index | archive | help
http://perforce.freebsd.org/chv.cgi?CH=135815 Change 135815 by rrs@rrs-mips2-jnpr on 2008/02/20 18:30:48 s9 indent, kill rest of // Affected files ... .. //depot/projects/mips2-jnpr/src/sys/mips/mips32/octeon32/octeon_pcmap_regs.h#4 edit Differences ... ==== //depot/projects/mips2-jnpr/src/sys/mips/mips32/octeon32/octeon_pcmap_regs.h#4 (text+ko) ==== @@ -49,68 +49,87 @@ #if defined(__mips_n32) || defined(__mips_n64) -static inline void oct_write64 (uint64_t csr_addr, uint64_t val64) +static inline void +oct_write64(uint64_t csr_addr, uint64_t val64) { - uint64_t *ptr = (uint64_t *) csr_addr; - *ptr = val64; + uint64_t *ptr = (uint64_t *) csr_addr; + + *ptr = val64; } -static inline void oct_write64_int64 (uint64_t csr_addr, int64_t val64i) +static inline void +oct_write64_int64(uint64_t csr_addr, int64_t val64i) { - int64_t *ptr = (int64_t *) csr_addr; - *ptr = val64; + int64_t *ptr = (int64_t *) csr_addr; + + *ptr = val64; } -static inline void oct_write8_x8 (uint64_t csr_addr, uint8_t val8) +static inline void +oct_write8_x8(uint64_t csr_addr, uint8_t val8) { - uint64_t *ptr = (uint64_t *) csr_addr; - *ptr = (uint64_t) val8; + uint64_t *ptr = (uint64_t *) csr_addr; + + *ptr = (uint64_t) val8; } -static inline void oct_write8 (uint64_t csr_addr, uint8_t val8) +static inline void +oct_write8(uint64_t csr_addr, uint8_t val8) { - oct_write64(csr_addr, (uint64_t) val8); + oct_write64(csr_addr, (uint64_t) val8); } -static inline void oct_write16 (uint64_t csr_addr, uint16_t val16) +static inline void +oct_write16(uint64_t csr_addr, uint16_t val16) { - oct_write64(csr_addr, (uint64_t) val16); + oct_write64(csr_addr, (uint64_t) val16); } -static inline void oct_write32 (uint64_t csr_addr, uint32_t val32) +static inline void +oct_write32(uint64_t csr_addr, uint32_t val32) { - oct_write64(csr_addr, (uint64_t) val32); + oct_write64(csr_addr, (uint64_t) val32); } -static inline uint8_t oct_read8 (uint64_t csr_addr) +static inline uint8_t +oct_read8(uint64_t csr_addr) { - uint8_t *ptr = (uint8_t *) csr_addr; - return (*ptr); + uint8_t *ptr = (uint8_t *) csr_addr; + + return (*ptr); } -static inline uint16_t oct_read16 (uint64_t csr_addr) +static inline uint16_t +oct_read16(uint64_t csr_addr) { - uint16_t *ptr = (uint16_t *) csr_addr; - return (*ptr); + uint16_t *ptr = (uint16_t *) csr_addr; + + return (*ptr); } -static inline uint32_t oct_read32 (uint64_t csr_addr) +static inline uint32_t +oct_read32(uint64_t csr_addr) { - uint32_t *ptr = (uint32_t *) csr_addr; - return (*ptr); + uint32_t *ptr = (uint32_t *) csr_addr; + + return (*ptr); } -static inline uint64_t oct_read64 (uint64_t csr_addr) +static inline uint64_t +oct_read64(uint64_t csr_addr) { - uint64_t *ptr = (uint64_t *) csr_addr; - return (*ptr); + uint64_t *ptr = (uint64_t *) csr_addr; + + return (*ptr); } -static inline int32_t oct_readint32 (uint64_t csr_addr) +static inline int32_t +oct_readint32(uint64_t csr_addr) { - int32_t *ptr = (int32_t *) csr_addr; - return (*ptr); + int32_t *ptr = (int32_t *) csr_addr; + + return (*ptr); } @@ -124,60 +143,62 @@ /* * Read/write functions */ -static inline void oct_write64 (uint64_t csr_addr, uint64_t val64) +static inline void +oct_write64(uint64_t csr_addr, uint64_t val64) { - uint32_t csr_addrh = csr_addr >> 32; - uint32_t csr_addrl = csr_addr; - uint32_t valh = (uint64_t)val64 >> 32; - uint32_t vall = val64; - uint32_t tmp1; - uint32_t tmp2; - uint32_t tmp3; + uint32_t csr_addrh = csr_addr >> 32; + uint32_t csr_addrl = csr_addr; + uint32_t valh = (uint64_t) val64 >> 32; + uint32_t vall = val64; + uint32_t tmp1; + uint32_t tmp2; + uint32_t tmp3; - __asm __volatile ( - ".set mips64\n" - "dsll %0, %3, 32\n" - "dsll %1, %5, 32\n" - "dsll %2, %4, 32\n" - "dsrl %2, %2, 32\n" - "or %0, %0, %2\n" - "dsll %2, %6, 32\n" - "dsrl %2, %2, 32\n" - "or %1, %1, %2\n" - "sd %0, 0(%1)\n" - ".set mips0\n" - : "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3) - : "r" (valh), "r" (vall), - "r" (csr_addrh), "r" (csr_addrl) - ); + __asm __volatile( + ".set mips64\n" + "dsll %0, %3, 32\n" + "dsll %1, %5, 32\n" + "dsll %2, %4, 32\n" + "dsrl %2, %2, 32\n" + "or %0, %0, %2\n" + "dsll %2, %6, 32\n" + "dsrl %2, %2, 32\n" + "or %1, %1, %2\n" + "sd %0, 0(%1)\n" + ".set mips0\n" + : "=&r"(tmp1), "=&r"(tmp2), "=&r"(tmp3) + : "r"(valh), "r"(vall), + "r"(csr_addrh), "r"(csr_addrl) + ); } -static inline void oct_write64_int64 (uint64_t csr_addr, int64_t val64i) +static inline void +oct_write64_int64(uint64_t csr_addr, int64_t val64i) { - uint32_t csr_addrh = csr_addr >> 32; - uint32_t csr_addrl = csr_addr; - int32_t valh = (uint64_t)val64i >> 32; - int32_t vall = val64i; - uint32_t tmp1; - uint32_t tmp2; - uint32_t tmp3; + uint32_t csr_addrh = csr_addr >> 32; + uint32_t csr_addrl = csr_addr; + int32_t valh = (uint64_t) val64i >> 32; + int32_t vall = val64i; + uint32_t tmp1; + uint32_t tmp2; + uint32_t tmp3; - __asm __volatile ( - ".set mips64\n" - "dsll %0, %3, 32\n" - "dsll %1, %5, 32\n" - "dsll %2, %4, 32\n" - "dsrl %2, %2, 32\n" - "or %0, %0, %2\n" - "dsll %2, %6, 32\n" - "dsrl %2, %2, 32\n" - "or %1, %1, %2\n" - "sd %0, 0(%1)\n" - ".set mips0\n" - : "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3) - : "r" (valh), "r" (vall), - "r" (csr_addrh), "r" (csr_addrl) - ); + __asm __volatile( + ".set mips64\n" + "dsll %0, %3, 32\n" + "dsll %1, %5, 32\n" + "dsll %2, %4, 32\n" + "dsrl %2, %2, 32\n" + "or %0, %0, %2\n" + "dsll %2, %6, 32\n" + "dsrl %2, %2, 32\n" + "or %1, %1, %2\n" + "sd %0, 0(%1)\n" + ".set mips0\n" + : "=&r"(tmp1), "=&r"(tmp2), "=&r"(tmp3) + : "r"(valh), "r"(vall), + "r"(csr_addrh), "r"(csr_addrl) + ); } @@ -186,23 +207,24 @@ * * 8 bit data write into IO Space. Written using an 8 bit bus io transaction */ -static inline void oct_write8_x8 (uint64_t csr_addr, uint8_t val8) +static inline void +oct_write8_x8(uint64_t csr_addr, uint8_t val8) { - uint32_t csr_addrh = csr_addr>>32; - uint32_t csr_addrl = csr_addr; - uint32_t tmp1; - uint32_t tmp2; + uint32_t csr_addrh = csr_addr >> 32; + uint32_t csr_addrl = csr_addr; + uint32_t tmp1; + uint32_t tmp2; - __asm __volatile ( - ".set mips64\n" - "dsll %0, %3, 32\n" - "dsll %1, %4, 32\n" - "dsrl %1, %1, 32\n" - "or %0, %0, %1\n" - "sb %2, 0(%0)\n" - ".set mips0\n" - : "=&r" (tmp1), "=&r" (tmp2) - : "r" (val8), "r" (csr_addrh), "r" (csr_addrl) ); + __asm __volatile( + ".set mips64\n" + "dsll %0, %3, 32\n" + "dsll %1, %4, 32\n" + "dsrl %1, %1, 32\n" + "or %0, %0, %1\n" + "sb %2, 0(%0)\n" + ".set mips0\n" + : "=&r"(tmp1), "=&r"(tmp2) + : "r"(val8), "r"(csr_addrh), "r"(csr_addrl)); } /* @@ -210,182 +232,198 @@ * * 8 bit data write into IO Space. Written using a 64 bit bus io transaction */ -static inline void oct_write8 (uint64_t csr_addr, uint8_t val8) +static inline void +oct_write8(uint64_t csr_addr, uint8_t val8) { #if 0 - oct_write64(csr_addr, (uint64_t) val8); + oct_write64(csr_addr, (uint64_t) val8); #else - uint32_t csr_addrh = csr_addr>>32; - uint32_t csr_addrl = csr_addr; - uint32_t tmp1; - uint32_t tmp2; + uint32_t csr_addrh = csr_addr >> 32; + uint32_t csr_addrl = csr_addr; + uint32_t tmp1; + uint32_t tmp2; + + __asm __volatile( + ".set mips64\n" + "dsll %0, %3, 32\n" + "dsll %1, %4, 32\n" + "dsrl %1, %1, 32\n" + "or %0, %0, %1\n" + "sb %2, 0(%0)\n" + ".set mips0\n" + : "=&r"(tmp1), "=&r"(tmp2) + : "r"(val8), "r"(csr_addrh), "r"(csr_addrl)); - __asm __volatile ( - ".set mips64\n" - "dsll %0, %3, 32\n" - "dsll %1, %4, 32\n" - "dsrl %1, %1, 32\n" - "or %0, %0, %1\n" - "sb %2, 0(%0)\n" - ".set mips0\n" - : "=&r" (tmp1), "=&r" (tmp2) - : "r" (val8), "r" (csr_addrh), "r" (csr_addrl) ); #endif } -static inline void oct_write16 (uint64_t csr_addr, uint16_t val16) +static inline void +oct_write16(uint64_t csr_addr, uint16_t val16) { #if 0 - oct_write64(csr_addr, (uint64_t) val16); + oct_write64(csr_addr, (uint64_t) val16); #else - uint32_t csr_addrh = csr_addr>>32; - uint32_t csr_addrl = csr_addr; - uint32_t tmp1; - uint32_t tmp2; + uint32_t csr_addrh = csr_addr >> 32; + uint32_t csr_addrl = csr_addr; + uint32_t tmp1; + uint32_t tmp2; + + __asm __volatile( + ".set mips64\n" + "dsll %0, %3, 32\n" + "dsll %1, %4, 32\n" + "dsrl %1, %1, 32\n" + "or %0, %0, %1\n" + "sh %2, 0(%0)\n" + ".set mips0\n" + : "=&r"(tmp1), "=&r"(tmp2) + : "r"(val16), "r"(csr_addrh), "r"(csr_addrl)); - __asm __volatile ( - ".set mips64\n" - "dsll %0, %3, 32\n" - "dsll %1, %4, 32\n" - "dsrl %1, %1, 32\n" - "or %0, %0, %1\n" - "sh %2, 0(%0)\n" - ".set mips0\n" - : "=&r" (tmp1), "=&r" (tmp2) - : "r" (val16), "r" (csr_addrh), "r" (csr_addrl) ); #endif } -static inline void oct_write32 (uint64_t csr_addr, uint32_t val32) +static inline void +oct_write32(uint64_t csr_addr, uint32_t val32) { -#if 0 - oct_write64(csr_addr, (uint64_t) val32); +#if 0 + oct_write64(csr_addr, (uint64_t) val32); #else - uint32_t csr_addrh = csr_addr>>32; - uint32_t csr_addrl = csr_addr; - uint32_t tmp1; - uint32_t tmp2; + uint32_t csr_addrh = csr_addr >> 32; + uint32_t csr_addrl = csr_addr; + uint32_t tmp1; + uint32_t tmp2; + + __asm __volatile( + ".set mips64\n" + "dsll %0, %3, 32\n" + "dsll %1, %4, 32\n" + "dsrl %1, %1, 32\n" + "or %0, %0, %1\n" + "sw %2, 0(%0)\n" + ".set mips0\n" + : "=&r"(tmp1), "=&r"(tmp2) + : "r"(val32), "r"(csr_addrh), "r"(csr_addrl)); - __asm __volatile ( - ".set mips64\n" - "dsll %0, %3, 32\n" - "dsll %1, %4, 32\n" - "dsrl %1, %1, 32\n" - "or %0, %0, %1\n" - "sw %2, 0(%0)\n" - ".set mips0\n" - : "=&r" (tmp1), "=&r" (tmp2) - : "r" (val32), "r" (csr_addrh), "r" (csr_addrl) ); #endif } -static inline uint8_t oct_read8 (uint64_t csr_addr) +static inline uint8_t +oct_read8(uint64_t csr_addr) { - uint32_t csr_addrh = csr_addr>>32; - uint32_t csr_addrl = csr_addr; - uint32_t tmp1, tmp2; + uint32_t csr_addrh = csr_addr >> 32; + uint32_t csr_addrl = csr_addr; + uint32_t tmp1, tmp2; + + __asm __volatile( + ".set mips64\n" + "dsll %1, %2, 32\n" + "dsll %0, %3, 32\n" + "dsrl %0, %0, 32\n" + "or %1, %1, %0\n" + "lb %1, 0(%1)\n" + ".set mips0\n" + : "=&r"(tmp1), "=&r"(tmp2) + : "r"(csr_addrh), "r"(csr_addrl)); - __asm __volatile ( - ".set mips64\n" - "dsll %1, %2, 32\n" - "dsll %0, %3, 32\n" - "dsrl %0, %0, 32\n" - "or %1, %1, %0\n" - "lb %1, 0(%1)\n" - ".set mips0\n" - : "=&r" (tmp1), "=&r" (tmp2) - : "r" (csr_addrh), "r" (csr_addrl) ); - return ((uint8_t) tmp2); + return ((uint8_t) tmp2); } -static inline uint16_t oct_read16 (uint64_t csr_addr) +static inline uint16_t +oct_read16(uint64_t csr_addr) { - uint32_t csr_addrh = csr_addr>>32; - uint32_t csr_addrl = csr_addr; - uint32_t tmp1, tmp2; + uint32_t csr_addrh = csr_addr >> 32; + uint32_t csr_addrl = csr_addr; + uint32_t tmp1, tmp2; + + __asm __volatile( + ".set mips64\n" + "dsll %1, %2, 32\n" + "dsll %0, %3, 32\n" + "dsrl %0, %0, 32\n" + "or %1, %1, %0\n" + "lh %1, 0(%1)\n" + ".set mips0\n" + : "=&r"(tmp1), "=&r"(tmp2) + : "r"(csr_addrh), "r"(csr_addrl)); - __asm __volatile ( - ".set mips64\n" - "dsll %1, %2, 32\n" - "dsll %0, %3, 32\n" - "dsrl %0, %0, 32\n" - "or %1, %1, %0\n" - "lh %1, 0(%1)\n" - ".set mips0\n" - : "=&r" (tmp1), "=&r" (tmp2) - : "r" (csr_addrh), "r" (csr_addrl) ); - return ((uint16_t) tmp2); + return ((uint16_t) tmp2); } -static inline uint32_t oct_read32 (uint64_t csr_addr) +static inline uint32_t +oct_read32(uint64_t csr_addr) { - uint32_t csr_addrh = csr_addr>>32; - uint32_t csr_addrl = csr_addr; - uint32_t val32; - uint32_t tmp; + uint32_t csr_addrh = csr_addr >> 32; + uint32_t csr_addrl = csr_addr; + uint32_t val32; + uint32_t tmp; + + __asm __volatile( + ".set mips64\n" + "dsll %0, %2, 32\n" + "dsll %1, %3, 32\n" + "dsrl %1, %1, 32\n" + "or %0, %0, %1\n" + "lw %0, 0(%0)\n" + ".set mips0\n" + : "=&r"(val32), "=&r"(tmp) + : "r"(csr_addrh), "r"(csr_addrl)); - __asm __volatile ( - ".set mips64\n" - "dsll %0, %2, 32\n" - "dsll %1, %3, 32\n" - "dsrl %1, %1, 32\n" - "or %0, %0, %1\n" - "lw %0, 0(%0)\n" - ".set mips0\n" - : "=&r" (val32), "=&r" (tmp) - : "r" (csr_addrh), "r" (csr_addrl) ); - return (val32); + return (val32); } -static inline uint64_t oct_read64 (uint64_t csr_addr) +static inline uint64_t +oct_read64(uint64_t csr_addr) { - uint32_t csr_addrh = csr_addr >> 32; - uint32_t csr_addrl = csr_addr; - uint32_t valh; - uint32_t vall; + uint32_t csr_addrh = csr_addr >> 32; + uint32_t csr_addrl = csr_addr; + uint32_t valh; + uint32_t vall; + + __asm __volatile( + ".set mips64\n" + "dsll %0, %2, 32\n" + "dsll %1, %3, 32\n" + "dsrl %1, %1, 32\n" + "or %0, %0, %1\n" + "ld %1, 0(%0)\n" + "dsrl %0, %1, 32\n" + "dsll %1, %1, 32\n" + "dsrl %1, %1, 32\n" + ".set mips0\n" + : "=&r"(valh), "=&r"(vall) + : "r"(csr_addrh), "r"(csr_addrl) + ); - __asm __volatile ( - ".set mips64\n" - "dsll %0, %2, 32\n" - "dsll %1, %3, 32\n" - "dsrl %1, %1, 32\n" - "or %0, %0, %1\n" - "ld %1, 0(%0)\n" - "dsrl %0, %1, 32\n" - "dsll %1, %1, 32\n" - "dsrl %1, %1, 32\n" - ".set mips0\n" - : "=&r" (valh), "=&r" (vall) - : "r" (csr_addrh), "r" (csr_addrl) - ); - return ((uint64_t)valh << 32) | vall; + return ((uint64_t) valh << 32) | vall; } -static inline int32_t oct_readint32 (uint64_t csr_addr) +static inline int32_t +oct_readint32(uint64_t csr_addr) { - uint32_t csr_addrh = csr_addr>>32; - uint32_t csr_addrl = csr_addr; - int32_t val32; - uint32_t tmp; + uint32_t csr_addrh = csr_addr >> 32; + uint32_t csr_addrl = csr_addr; + int32_t val32; + uint32_t tmp; + + __asm __volatile( + ".set mips64\n" + "dsll %0, %2, 32\n" + "dsll %1, %3, 32\n" + "dsrl %1, %1, 32\n" + "or %0, %0, %1\n" + "lw %0, 0(%0)\n" + : "=&r"(val32), "=&r"(tmp) + : "r"(csr_addrh), "r"(csr_addrl)); - __asm __volatile ( - ".set mips64\n" - "dsll %0, %2, 32\n" - "dsll %1, %3, 32\n" - "dsrl %1, %1, 32\n" - "or %0, %0, %1\n" - "lw %0, 0(%0)\n" - : "=&r" (val32), "=&r" (tmp) - : "r" (csr_addrh), "r" (csr_addrl) ); - return (val32); + return (val32); } @@ -393,7 +431,7 @@ #define OCTEON_HW_BASE ((volatile uint64_t *) 0L) -#define OCTEON_REG_OFFSET (-4 * 1024ll) /* local scratchpad reg base */ +#define OCTEON_REG_OFFSET (-4 * 1024ll) /* local scratchpad reg base */ #define OCTEON_SCRATCH_BASE ((volatile uint8_t *)(OCTEON_HW_BASE + \ OCTEON_REG_OFFSET)) @@ -403,19 +441,21 @@ #define OCTEON_SCRATCH_2 32 -static inline uint64_t oct_mf_chord (void) +static inline uint64_t +oct_mf_chord(void) { - uint64_t dest; + uint64_t dest; + + __asm __volatile(".set push\n" + ".set noreorder\n" + ".set noat\n" + ".set mips64\n" + "dmfc2 $1, 0x400\n" + "move %0, $1\n" + ".set pop\n" + : "=r"(dest)::"$1"); - __asm __volatile ( ".set push\n" - ".set noreorder\n" - ".set noat\n" - ".set mips64\n" - "dmfc2 $1, 0x400\n" - "move %0, $1\n" - ".set pop\n" - : "=r" (dest) : : "$1"); - return dest; + return dest; } @@ -485,14 +525,16 @@ ".set mips0\n" \ : "=&r" (dest) : ) -static inline uint64_t oct_scratch_read64 (uint64_t address) +static inline uint64_t +oct_scratch_read64(uint64_t address) { - return(*((volatile uint64_t *)(OCTEON_SCRATCH_BASE + address))); + return (*((volatile uint64_t *)(OCTEON_SCRATCH_BASE + address))); } -static inline void oct_scratch_write64 (uint64_t address, uint64_t value) +static inline void +oct_scratch_write64(uint64_t address, uint64_t value) { - *((volatile uint64_t *)(OCTEON_SCRATCH_BASE + address)) = value; + *((volatile uint64_t *)(OCTEON_SCRATCH_BASE + address)) = value; } @@ -511,17 +553,17 @@ * Octeon Address Space Definitions */ typedef enum { - OCTEON_MIPS_SPACE_XKSEG = 3LL, - OCTEON_MIPS_SPACE_XKPHYS = 2LL, - OCTEON_MIPS_SPACE_XSSEG = 1LL, - OCTEON_MIPS_SPACE_XUSEG = 0LL + OCTEON_MIPS_SPACE_XKSEG = 3LL, + OCTEON_MIPS_SPACE_XKPHYS = 2LL, + OCTEON_MIPS_SPACE_XSSEG = 1LL, + OCTEON_MIPS_SPACE_XUSEG = 0LL } octeon_mips_space_t; typedef enum { - OCTEON_MIPS_XKSEG_SPACE_KSEG0 = 0LL, - OCTEON_MIPS_XKSEG_SPACE_KSEG1 = 1LL, - OCTEON_MIPS_XKSEG_SPACE_SSEG = 2LL, - OCTEON_MIPS_XKSEG_SPACE_KSEG3 = 3LL + OCTEON_MIPS_XKSEG_SPACE_KSEG0 = 0LL, + OCTEON_MIPS_XKSEG_SPACE_KSEG1 = 1LL, + OCTEON_MIPS_XKSEG_SPACE_SSEG = 2LL, + OCTEON_MIPS_XKSEG_SPACE_KSEG3 = 3LL } octeon_mips_xkseg_space_t; @@ -535,9 +577,9 @@ * We limit the allocated device physical blocks to low mem. So use Kseg0 */ -//#ifdef PTR_SIZE == sizeof(u_int32) +/*#ifdef PTR_SIZE == sizeof(u_int32)*/ #define OCTEON_PHYS2PTR(addr) ((void *) (((uint32_t) addr) | 0x80000000)) -//#endif +/*#endif*/ #if 0 #ifdef PTR_SIZE == sizeof(u_int64) @@ -553,13 +595,13 @@ #define OCTEON_PTR2PHYS(addr) octeon_ptr_to_phys(addr) -//#ifdef PTR_SIZE == sizeof(uint32_t) +/*#ifdef PTR_SIZE == sizeof(uint32_t)*/ -#define mipsx_addr_size uint32_t // u_int64 -#define MIPSX_ADDR_SIZE_KSEGX_BIT_SHIFT 30 // 62 -#define MIPSX_ADDR_SIZE_KSEGX_MASK_REMOVED 0x1fffffff // 0x1fffffff +#define mipsx_addr_size uint32_t /* u_int64 */ +#define MIPSX_ADDR_SIZE_KSEGX_BIT_SHIFT 30 /* 62 */ +#define MIPSX_ADDR_SIZE_KSEGX_MASK_REMOVED 0x1fffffff /* 0x1fffffff */ -//#endif +/*#endif*/ #if 0 #ifdef PTR_SIZE == sizeof(uint64_t) @@ -577,20 +619,22 @@ #if 0 -static inline mipsx_addr_size octeon_ptr_to_phys (void *ptr) +static inline mipsx_addr_size +octeon_ptr_to_phys(void *ptr) { - if ((((mipsx_addr_size) ptr) >> MIPSX_ADDR_SIZE_KSEGX_BIT_SHIFT) == 2) { - /* - * KSEG0 based address ? - */ - return ((mipsx_addr_size) ptr & MIPSX_ADDR_SIZE_KSEGX_MASK_REMOVED); - } else { - /* - * Ask kernel/vm to give us the phys translation. - */ - return (vtophys(ptr)); - } + if ((((mipsx_addr_size) ptr) >> MIPSX_ADDR_SIZE_KSEGX_BIT_SHIFT) == 2) { + /* + * KSEG0 based address ? + */ + return ((mipsx_addr_size) ptr & MIPSX_ADDR_SIZE_KSEGX_MASK_REMOVED); + } else { + /* + * Ask kernel/vm to give us the phys translation. + */ + return (vtophys(ptr)); + } } + #endif #define OCTEON_IO_SEG OCTEON_MIPS_SPACE_XKPHYS @@ -614,69 +658,77 @@ * octeon_addr_t */ typedef union { - uint64_t word64; + uint64_t word64; - struct { - octeon_mips_space_t R : 2; - uint64_t offset :62; - } sva; // mapped or unmapped virtual address + struct { + octeon_mips_space_t R:2; + uint64_t offset:62; + } sva; /* mapped or unmapped virtual address */ - struct { - uint64_t zeroes :33; - uint64_t offset :31; - } suseg; // mapped USEG virtual addresses (typically) + struct { + uint64_t zeroes:33; + uint64_t offset:31; + } suseg; /* mapped USEG virtual addresses (typically) */ - struct { - uint64_t ones :33; - octeon_mips_xkseg_space_t sp : 2; - uint64_t offset :29; - } sxkseg; // mapped or unmapped virtual address + struct { + uint64_t ones:33; + octeon_mips_xkseg_space_t sp:2; + uint64_t offset:29; + } sxkseg; /* mapped or unmapped virtual address */ - struct { - octeon_mips_space_t R :2; // CVMX_MIPS_SPACE_XKPHYS in this case - uint64_t cca : 3; // ignored by octeon - uint64_t mbz :10; - uint64_t pa :49; // physical address - } sxkphys; // physical address accessed through xkphys unmapped virtual address + struct { + octeon_mips_space_t R:2; /* CVMX_MIPS_SPACE_XKPHYS in + * this case */ + uint64_t cca:3; /* ignored by octeon */ + uint64_t mbz:10; + uint64_t pa:49; /* physical address */ + } sxkphys; /* physical address accessed through xkphys + * unmapped virtual address */ - struct { - uint64_t mbz :15; - uint64_t is_io : 1; // if set, the address is uncached and resides on MCB bus - uint64_t did : 8; // the hardware ignores this field when is_io==0, else device ID - uint64_t unaddr: 4; // the hardware ignores <39:36> in Octeon I - uint64_t offset :36; - } sphys; // physical address + struct { + uint64_t mbz:15; + uint64_t is_io:1; /* if set, the address is uncached and + * resides on MCB bus */ + uint64_t did:8; /* the hardware ignores this field when + * is_io==0, else device ID */ + uint64_t unaddr:4; /* the hardware ignores <39:36> in + * Octeon I */ + uint64_t offset:36; + } sphys; /* physical address */ - struct { - uint64_t zeroes :24; // techically, <47:40> are dont-cares - uint64_t unaddr: 4; // the hardware ignores <39:36> in Octeon I - uint64_t offset :36; - } smem; // physical mem address + struct { + uint64_t zeroes:24; /* techically, <47:40> are dont-cares */ + uint64_t unaddr:4; /* the hardware ignores <39:36> in + * Octeon I */ + uint64_t offset:36; + } smem; /* physical mem address */ - struct { - uint64_t mem_region :2; - uint64_t mbz :13; - uint64_t is_io : 1; // 1 in this case - uint64_t did : 8; // the hardware ignores this field when is_io==0, else device ID - uint64_t unaddr: 4; // the hardware ignores <39:36> in Octeon I - uint64_t offset :36; - } sio; // physical IO address + struct { + uint64_t mem_region:2; + uint64_t mbz:13; + uint64_t is_io:1; /* 1 in this case */ + uint64_t did:8; /* the hardware ignores this field when + * is_io==0, else device ID */ + uint64_t unaddr:4; /* the hardware ignores <39:36> in + * Octeon I */ + uint64_t offset:36; + } sio; /* physical IO address */ - struct { - uint64_t didspace : 24; - uint64_t unused : 40; - } sfilldidspace; + struct { + uint64_t didspace:24; + uint64_t unused:40; + } sfilldidspace; -} octeon_addr_t; +} octeon_addr_t; typedef union { - uint64_t word64; - struct { - uint32_t word32hi; - uint32_t word32lo; - } bits; -} octeon_word_t; + uint64_t word64; + struct { + uint32_t word32hi; + uint32_t word32lo; + } bits; +} octeon_word_t; @@ -686,10 +738,11 @@ * * Builds a memory address for I/O based on the Major 5bits and Sub DID 3bits */ -static inline uint64_t octeon_build_io_address (uint64_t major_did, - uint64_t sub_did) +static inline uint64_t +octeon_build_io_address(uint64_t major_did, + uint64_t sub_did) { - return ((0x1ull << 48) | (major_did << 43) | (sub_did << 40)); + return ((0x1ull << 48) | (major_did << 43) | (sub_did << 40)); } /* @@ -700,9 +753,10 @@ * @param bits Number of bits in the mask * @return The mask */ -static inline uint64_t octeon_build_mask (uint64_t bits) +static inline uint64_t +octeon_build_mask(uint64_t bits) { - return ~((~0x0ull) << bits); + return ~((~0x0ull) << bits); } /* @@ -724,19 +778,20 @@ * @param value Value to use * @return Value masked and shifted */ -static inline uint64_t octeon_build_bits (uint64_t high_bit, uint64_t low_bit, - uint64_t value) +static inline uint64_t +octeon_build_bits(uint64_t high_bit, uint64_t low_bit, + uint64_t value) { - return ((value & octeon_build_mask(high_bit - low_bit + 1)) << low_bit); + return ((value & octeon_build_mask(high_bit - low_bit + 1)) << low_bit); } /********************** simple spinlocks ***************/ typedef struct { - volatile uint32_t value; -} octeon_spinlock_t; + volatile uint32_t value; +} octeon_spinlock_t; -// note - macros not expanded in inline ASM, so values hardcoded +/* note - macros not expanded in inline ASM, so values hardcoded */ #define OCTEON_SPINLOCK_UNLOCKED_VAL 0 #define OCTEON_SPINLOCK_LOCKED_VAL 1 @@ -745,21 +800,24 @@ * * @param lock Lock to initialize */ -static inline void octeon_spinlock_init(octeon_spinlock_t *lock) +static inline void +octeon_spinlock_init(octeon_spinlock_t * lock) { - lock->value = OCTEON_SPINLOCK_UNLOCKED_VAL; + lock->value = OCTEON_SPINLOCK_UNLOCKED_VAL; } + /** * Releases lock * * @param lock pointer to lock structure */ -static inline void octeon_spinlock_unlock(octeon_spinlock_t *lock) +static inline void +octeon_spinlock_unlock(octeon_spinlock_t * lock) { - OCTEON_SYNCWS; + OCTEON_SYNCWS; - lock->value = 0; - OCTEON_SYNCWS; + lock->value = 0; + OCTEON_SYNCWS; } /** @@ -767,21 +825,22 @@ * * @param lock pointer to lock structure */ -static inline void octeon_spinlock_lock(octeon_spinlock_t *lock) +static inline void +octeon_spinlock_lock(octeon_spinlock_t * lock) { - unsigned int tmp; - __asm __volatile( - ".set noreorder \n" - "1: ll %1, %0 \n" - " bnez %1, 1b \n" - " li %1, 1 \n" - " sc %1, %0 \n" - " beqz %1, 1b \n" - " nop \n" - ".set reorder \n" - : "+m" (lock->value), "=&r" (tmp ) - : >>> TRUNCATED FOR MAIL (1000 lines) <<<
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?200802201831.m1KIVYSr081473>