Date: Mon, 9 Jul 2012 07:31:27 +0000 (UTC) From: Adrian Chadd <adrian@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r238280 - in head/sys/dev/ath: . ath_hal Message-ID: <201207090731.q697VRQ6002836@svn.freebsd.org>
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Author: adrian Date: Mon Jul 9 07:31:26 2012 New Revision: 238280 URL: http://svn.freebsd.org/changeset/base/238280 Log: Introduce the EDMA related HAL capabilities. Whilst here, fix a typo in a previous commit. Obtained from: Qualcomm Atheros Modified: head/sys/dev/ath/ath_hal/ah.c head/sys/dev/ath/ath_hal/ah.h head/sys/dev/ath/if_athvar.h Modified: head/sys/dev/ath/ath_hal/ah.c ============================================================================== --- head/sys/dev/ath/ath_hal/ah.c Mon Jul 9 07:25:09 2012 (r238279) +++ head/sys/dev/ath/ath_hal/ah.c Mon Jul 9 07:31:26 2012 (r238280) @@ -619,6 +619,33 @@ ath_hal_getcapability(struct ath_hal *ah return pCap->hal4AddrAggrSupport ? HAL_OK : HAL_ENOTSUPP; case HAL_CAP_EXT_CHAN_DFS: return pCap->halExtChanDfsSupport ? HAL_OK : HAL_ENOTSUPP; + case HAL_CAP_NUM_TXMAPS: + *result = pCap->halNumTxMaps; + return HAL_OK; + case HAL_CAP_TXDESCLEN: + *result = pCap->halTxDescLen; + return HAL_OK; + case HAL_CAP_TXSTATUSLEN: + *result = pCap->halTxStatusLen; + return HAL_OK; + case HAL_CAP_RXSTATUSLEN: + *result = pCap->halRxStatusLen; + return HAL_OK; + case HAL_CAP_RXFIFODEPTH: + switch (capability) { + case HAL_RX_QUEUE_HP: + *result = pCap->halRxHpFifoDepth; + return HAL_OK; + case HAL_RX_QUEUE_LP: + *result = pCap->halRxLpFifoDepth; + return HAL_OK; + default: + return HAL_ENOTSUPP; + } + case HAL_CAP_RXBUFSIZE: + case HAL_CAP_NUM_MR_RETRIES: + return HAL_EINVAL; /* XXX not yet */ + case HAL_CAP_COMBINED_RADAR_RSSI: return pCap->halUseCombinedRadarRssi ? HAL_OK : HAL_ENOTSUPP; case HAL_CAP_AUTO_SLEEP: @@ -667,6 +694,8 @@ ath_hal_getcapability(struct ath_hal *ah return pCap->halHasBBReadWar? HAL_OK : HAL_ENOTSUPP; case HAL_CAP_SERIALISE_WAR: /* PCI register serialisation */ return pCap->halSerialiseRegWar ? HAL_OK : HAL_ENOTSUPP; + case HAL_CAP_ENHANCED_DMA_SUPPORT: + return pCap->halEnhancedDmaSupport ? HAL_OK : HAL_ENOTSUPP; default: return HAL_EINVAL; } Modified: head/sys/dev/ath/ath_hal/ah.h ============================================================================== --- head/sys/dev/ath/ath_hal/ah.h Mon Jul 9 07:25:09 2012 (r238279) +++ head/sys/dev/ath/ath_hal/ah.h Mon Jul 9 07:31:26 2012 (r238280) @@ -149,9 +149,14 @@ typedef enum { HAL_CAP_TS = 72, /* 3 stream */ HAL_CAP_ENHANCED_DMA_SUPPORT = 75, /* DMA FIFO support */ + HAL_CAP_NUM_TXMAPS = 76, /* Number of buffers in a transmit descriptor */ + HAL_CAP_TXDESCLEN = 77, /* Length of transmit descriptor */ + HAL_CAP_TXSTATUSLEN = 78, /* Length of transmit status descriptor */ + HAL_CAP_RXSTATUSLEN = 79, /* Length of transmit status descriptor */ + HAL_CAP_RXFIFODEPTH = 80, /* Receive hardware FIFO depth */ + HAL_CAP_RXBUFSIZE = 81, /* Receive Buffer Length */ + HAL_CAP_NUM_MR_RETRIES = 82, /* limit on multirate retries */ - HAL_CAP_RXBUFSIZE = 81, - HAL_CAP_NUM_MR_RETRIES = 82, HAL_CAP_OL_PWRCTRL = 84, /* Open loop TX power control */ HAL_CAP_BB_PANIC_WATCHDOG = 92, @@ -210,7 +215,7 @@ typedef enum { typedef enum { HAL_RX_QUEUE_HP = 0, /* high priority recv queue */ - HAL_RX_QUEUE_LP = 0, /* low priority recv queue */ + HAL_RX_QUEUE_LP = 1, /* low priority recv queue */ } HAL_RX_QUEUE; #define HAL_NUM_RX_QUEUES 2 /* max possible # of queues */ Modified: head/sys/dev/ath/if_athvar.h ============================================================================== --- head/sys/dev/ath/if_athvar.h Mon Jul 9 07:25:09 2012 (r238279) +++ head/sys/dev/ath/if_athvar.h Mon Jul 9 07:31:26 2012 (r238280) @@ -953,11 +953,34 @@ void ath_intr(void *); #define ath_hal_setintmit(_ah, _v) \ ath_hal_setcapability(_ah, HAL_CAP_INTMIT, \ HAL_CAP_INTMIT_ENABLE, _v, NULL) + +/* EDMA definitions */ #define ath_hal_hasedma(_ah) \ (ath_hal_getcapability(_ah, HAL_CAP_ENHANCED_DMA_SUPPORT, \ 0, NULL) == HAL_OK) +#define ath_hal_getrxfifodepth(_ah, _qtype, _req) \ + (ath_hal_getcapability(_ah, HAL_CAP_RXFIFODEPTH, _qtype, _req) \ + == HAL_OK) +#define ath_hal_getntxmaps(_ah, _req) \ + (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXMAPS, 0, _req) \ + == HAL_OK) +#define ath_hal_gettxdesclen(_ah, _req) \ + (ath_hal_getcapability(_ah, HAL_CAP_TXDESCLEN, 0, _req) \ + == HAL_OK) +#define ath_hal_gettxstatuslen(_ah, _req) \ + (ath_hal_getcapability(_ah, HAL_CAP_TXSTATUSLEN, 0, _req) \ + == HAL_OK) +#define ath_hal_getrxstatuslen(_ah, _req) \ + (ath_hal_getcapability(_ah, HAL_CAP_RXSTATUSLEN, 0, _req) \ + == HAL_OK) +#define ath_hal_setrxbufsize(_ah, _req) \ + (ath_hal_setcapability(_ah, HAL_CAP_RXBUFSIZE, 0, _req, NULL) \ + == HAL_OK) + #define ath_hal_getchannoise(_ah, _c) \ ((*(_ah)->ah_getChanNoise)((_ah), (_c))) + +/* 802.11n HAL methods */ #define ath_hal_getrxchainmask(_ah, _prxchainmask) \ (ath_hal_getcapability(_ah, HAL_CAP_RX_CHAINMASK, 0, _prxchainmask)) #define ath_hal_gettxchainmask(_ah, _ptxchainmask) \
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