Date: Thu, 23 Aug 2012 16:36:45 -0700 From: Adrian Chadd <adrian@freebsd.org> To: Ian Lepore <freebsd@damnhippie.dyndns.org> Cc: freebsd-arm@freebsd.org, freebsd-mips@freebsd.org, freebsd-arch@freebsd.org Subject: Re: Partial cacheline flush problems on ARM and MIPS Message-ID: <CAJ-Vmo=20OvDmndjGWsZXRKDC3xAJF4EdVzmHEOAq%2BxU5vgfaA@mail.gmail.com> In-Reply-To: <1345764428.27688.591.camel@revolution.hippie.lan> References: <1345757300.27688.535.camel@revolution.hippie.lan> <CAJ-VmokuY0WGYfKyBR_zemZnEuE=X04Z0y_rUpmWB-qY_N68Jw@mail.gmail.com> <1345764428.27688.591.camel@revolution.hippie.lan>
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Right, that's what Linux does for ARM/MIPS. It just sets the minimum allocation size to be cache line sized. That way they didn't have to fix their USB and network stack code. .. or, we could fix the USB stack code by saying that anything being used as a DMA buffer needs to be minimum cache line size (which can be determined at run time if appropriate) and make the minimum allocation that. Then either it uses a separate allocation for each buffer or it allocates one big set of buffers and chops them up in at least "cache line size" bits. That reminds me, I should do that to the descriptor allocation in the Atheros driver - ie, round up the descriptor allocation size to a multiple of a cache line. That way DMAs don't conflict with the next DMAed buffer.. Adrian
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