Date: Tue, 17 Sep 2002 10:23:51 +0200 (CEST) From: Harti Brandt <brandt@fokus.gmd.de> To: Poul-Henning Kamp <phk@critter.freebsd.dk> Cc: Archie Cobbs <archie@dellroad.org>, Bruce Evans <bde@zeta.org.au>, Josef Karthauser <joe@FreeBSD.ORG>, "David O'Brien" <obrien@FreeBSD.ORG>, <cvs-committers@FreeBSD.ORG>, <cvs-all@FreeBSD.ORG> Subject: Re: cvs commit: src/sys/kern kern_timeout.c Message-ID: <20020917100940.U812-200000@beagle.fokus.gmd.de> In-Reply-To: <84439.1032204014@critter.freebsd.dk>
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[-- Attachment #1 --] Hi, I just took the opportunity and to analyze the xl_mii_readreg routine that is one of the timeout hogs (through mii_tick). Instead of making DELAY(1) to do the right thing (which seems a rather complex task) I tried to find a local solution and did the following: (1) replaced all calls to DELAY(1) with a bus_space_read_4() on a card address. Because there are 184 DELAY(1) calls in each xl_mii_readreg each of which takes a mean of 8.5usecs this cuts down the overall time from 1.8msec to around 320usecs. (2) two macros MII_SET and MII_CLR are used to fiddle with the MDIO bits. This looks fine from an aesthetic standpoint of view, but adds some dozens of additional operations. I introduced a MII_SETCLR macro which can set and clear bits at the same time. This reduces the readreg time further to 250usecs. Because each mii_tick takes approx. 4 readregs this is still a lot, but better than before. Perhaps you could have a look at the patch that I have attached. Regards, harti -- harti brandt, http://www.fokus.gmd.de/research/cc/cats/employees/hartmut.brandt/private brandt@fokus.gmd.de, brandt@fokus.fhg.de [-- Attachment #2 --] Index: if_xl.c =================================================================== RCS file: /usr/ncvs/src/sys/pci/if_xl.c,v retrieving revision 1.105 diff -u -r1.105 if_xl.c --- if_xl.c 24 Aug 2002 00:02:03 -0000 1.105 +++ if_xl.c 16 Sep 2002 14:00:55 -0000 @@ -356,6 +356,16 @@ CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~x) +#define MII_SETCLR(x,y) \ + CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ + (CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~y) | x) + +static __inline void +xl_mii_delay(struct xl_softc *sc, u_int addr) +{ + CSR_READ_4(sc, addr); +} + /* * Sync the PHYs by setting data bit and strobing the clock 32 times. */ @@ -370,9 +380,9 @@ for (i = 0; i < 32; i++) { MII_SET(XL_MII_CLK); - DELAY(1); + xl_mii_delay(sc, XL_W4_PHY_MGMT); MII_CLR(XL_MII_CLK); - DELAY(1); + xl_mii_delay(sc, XL_W4_PHY_MGMT); } return; @@ -390,18 +400,18 @@ int i; XL_SEL_WIN(4); - MII_CLR(XL_MII_CLK); + /* XXX MII_CLR(XL_MII_CLK); */ + /* XXX could join the MII_SET/CLR of data with the CLR of the clock */ for (i = (0x1 << (cnt - 1)); i; i >>= 1) { if (bits & i) { - MII_SET(XL_MII_DATA); + MII_SETCLR(XL_MII_DATA, XL_MII_CLK); } else { - MII_CLR(XL_MII_DATA); + MII_CLR((XL_MII_DATA | XL_MII_CLK)); } - DELAY(1); - MII_CLR(XL_MII_CLK); - DELAY(1); + xl_mii_delay(sc, XL_W4_PHY_MGMT); MII_SET(XL_MII_CLK); + xl_mii_delay(sc, XL_W4_PHY_MGMT); } } @@ -433,11 +443,6 @@ XL_SEL_WIN(4); CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0); - /* - * Turn on data xmit. - */ - MII_SET(XL_MII_DIR); - xl_mii_sync(sc); /* @@ -448,20 +453,20 @@ xl_mii_send(sc, frame->mii_phyaddr, 5); xl_mii_send(sc, frame->mii_regaddr, 5); - /* Idle bit */ - MII_CLR((XL_MII_CLK|XL_MII_DATA)); - DELAY(1); - MII_SET(XL_MII_CLK); - DELAY(1); - /* Turn off xmit. */ MII_CLR(XL_MII_DIR); + /* turnaround */ + MII_CLR((XL_MII_CLK|XL_MII_DATA)); + xl_mii_delay(sc, XL_W4_PHY_MGMT); + MII_SET(XL_MII_CLK); + xl_mii_delay(sc, XL_W4_PHY_MGMT); + /* Check for ack */ MII_CLR(XL_MII_CLK); - DELAY(1); + xl_mii_delay(sc, XL_W4_PHY_MGMT); MII_SET(XL_MII_CLK); - DELAY(1); + xl_mii_delay(sc, XL_W4_PHY_MGMT); ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA; /* @@ -471,31 +476,29 @@ if (ack) { for(i = 0; i < 16; i++) { MII_CLR(XL_MII_CLK); - DELAY(1); + xl_mii_delay(sc, XL_W4_PHY_MGMT); MII_SET(XL_MII_CLK); - DELAY(1); + xl_mii_delay(sc, XL_W4_PHY_MGMT); } goto fail; } for (i = 0x8000; i; i >>= 1) { MII_CLR(XL_MII_CLK); - DELAY(1); - if (!ack) { - if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA) - frame->mii_data |= i; - DELAY(1); - } + xl_mii_delay(sc, XL_W4_PHY_MGMT); + if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA) + frame->mii_data |= i; MII_SET(XL_MII_CLK); - DELAY(1); + xl_mii_delay(sc, XL_W4_PHY_MGMT); } fail: + /* Idle bit */ MII_CLR(XL_MII_CLK); - DELAY(1); + xl_mii_delay(sc, XL_W4_PHY_MGMT); MII_SET(XL_MII_CLK); - DELAY(1); + xl_mii_delay(sc, XL_W4_PHY_MGMT); XL_UNLOCK(sc); @@ -544,9 +547,9 @@ /* Idle bit. */ MII_SET(XL_MII_CLK); - DELAY(1); + xl_mii_delay(sc, XL_W4_PHY_MGMT); MII_CLR(XL_MII_CLK); - DELAY(1); + xl_mii_delay(sc, XL_W4_PHY_MGMT); /* * Turn off xmit.home | help
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