Date: Sun, 8 May 2005 23:05:03 GMT From: Marcel Moolenaar <marcel@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 76713 for review Message-ID: <200505082305.j48N53v3007036@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=76713 Change 76713 by marcel@marcel_nfs on 2005/05/08 23:04:54 Initialization step 2b+3: Reprogram the graphics controller, reprogram the attribute controller and clear the frame buffer. While here again: Wait for the vertical retrace before we pull the sync. signals off the cable. This has 2 purposes; 1) it avoids flicker and 2) it makes sure the internal flip-flop of the attribute controller is reset. At this point, when the VGA is probed and is not the console, the display clears and we're in graphics mode. Time for the visual feedback of this -- show a beastie logo... Affected files ... .. //depot/projects/tty/sys/dev/vga/vga.c#8 edit Differences ... ==== //depot/projects/tty/sys/dev/vga/vga.c#8 (text+ko) ==== @@ -63,20 +63,38 @@ x = REG_READ(sc, VGA_GEN_MISC_OUTPUT_R); REG_WRITE(sc, VGA_GEN_MISC_OUTPUT_W, x | VGA_GEN_MO_IOA); + /* + * Wait for the vertical retrace. + * NOTE: this code reads the VGA_GEN_INPUT_STAT_1 register, which has + * the side-effect of clearing the internal flip-flip of the attribute + * controller's write register. This means that because this code is + * here, we know for sure that the first write to the attribute + * controller will be a write to the address register. Removing this + * code therefore also removes that guarantee and appropriate measures + * need to be taken. + */ + do { + x = REG_READ(sc, VGA_GEN_INPUT_STAT_1); + x &= VGA_GEN_IS1_VR | VGA_GEN_IS1_DE; + } while (x != (VGA_GEN_IS1_VR | VGA_GEN_IS1_DE)); + /* Now, disable the sync. signals. */ REG_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_MODE_CONTROL); x = REG_READ(sc, VGA_CRTC_DATA); REG_WRITE(sc, VGA_CRTC_DATA, x & ~VGA_CRTC_MC_HR); + /* + * Set the VGA adapter in mode 0x12 (640x480x16). + */ + /* Unprotect CRTC registers 0-7. */ REG_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_RETRACE_END); x = REG_READ(sc, VGA_CRTC_DATA); REG_WRITE(sc, VGA_CRTC_DATA, x & ~VGA_CRTC_VRE_PR); /* - * Set the VGA adapter in mode 0x12 (640x480x16). + * Reprogram the CRTC. */ - /* Reprogram the CRTC. */ REG_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_HORIZ_TOTAL); REG_WRITE(sc, VGA_CRTC_DATA, 0x5f); /* 760 */ REG_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_HORIZ_DISP_END); @@ -129,11 +147,17 @@ VGA_CRTC_MC_SRS | VGA_CRTC_MC_CMS); REG_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_LINE_COMPARE); REG_WRITE(sc, VGA_CRTC_DATA, 0xff); /* 480 + 31 */ - /* Reprogram the general registers. */ + + /* + * Reprogram the general registers. + */ REG_WRITE(sc, VGA_GEN_MISC_OUTPUT_W, VGA_GEN_MO_VSP | VGA_GEN_MO_HSP | VGA_GEN_MO_PB | VGA_GEN_MO_ER | VGA_GEN_MO_IOA); REG_WRITE(sc, VGA_GEN_FEATURE_CTRL_W, 0); - /* Reprogram the sequencer. */ + + /* + * Reprogram the sequencer. + */ REG_WRITE(sc, VGA_SEQ_ADDRESS, VGA_SEQ_RESET); REG_WRITE(sc, VGA_SEQ_DATA, VGA_SEQ_RST_SR | VGA_SEQ_RST_NAR); REG_WRITE(sc, VGA_SEQ_ADDRESS, VGA_SEQ_CLOCKING_MODE); @@ -142,13 +166,95 @@ REG_WRITE(sc, VGA_SEQ_DATA, VGA_SEQ_MM_EM3 | VGA_SEQ_MM_EM2 | VGA_SEQ_MM_EM1 | VGA_SEQ_MM_EM0); REG_WRITE(sc, VGA_SEQ_ADDRESS, VGA_SEQ_CHAR_MAP_SELECT); - REG_WRITE(sc, VGA_SEQ_DATA, 0x0); + REG_WRITE(sc, VGA_SEQ_DATA, 0); REG_WRITE(sc, VGA_SEQ_ADDRESS, VGA_SEQ_MEMORY_MODE); REG_WRITE(sc, VGA_SEQ_DATA, VGA_SEQ_MM_OE | VGA_SEQ_MM_EM); - /* Reprogram the attribute controller. */ - /* Reprogram the graphics controller. */ + + /* + * Reprogram the attribute controller. The internal flip-flop is + * known to be clear and the next first will be to the address + * register. + */ + REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_PALETTE(0)); + REG_WRITE(sc, VGA_AC_WRITE, 0); + REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_PALETTE(1)); + REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_PAL_B); + REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_PALETTE(2)); + REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_PAL_G); + REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_PALETTE(3)); + REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_PAL_G | VGA_AC_PAL_B); + REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_PALETTE(4)); + REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_PAL_R); + REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_PALETTE(5)); + REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_PAL_R | VGA_AC_PAL_B); + REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_PALETTE(6)); + REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_PAL_SG | VGA_AC_PAL_R); + REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_PALETTE(7)); + REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_PAL_R | VGA_AC_PAL_G | VGA_AC_PAL_B); + REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_PALETTE(8)); + REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG | + VGA_AC_PAL_SB); + REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_PALETTE(9)); + REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG | + VGA_AC_PAL_SB | VGA_AC_PAL_B); + REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_PALETTE(10)); + REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG | + VGA_AC_PAL_SB | VGA_AC_PAL_G); + REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_PALETTE(11)); + REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG | + VGA_AC_PAL_SB | VGA_AC_PAL_G | VGA_AC_PAL_B); + REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_PALETTE(12)); + REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG | + VGA_AC_PAL_SB | VGA_AC_PAL_R); + REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_PALETTE(13)); + REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG | + VGA_AC_PAL_SB | VGA_AC_PAL_R | VGA_AC_PAL_B); + REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_PALETTE(14)); + REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG | + VGA_AC_PAL_SB | VGA_AC_PAL_R | VGA_AC_PAL_G); + REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_PALETTE(15)); + REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG | + VGA_AC_PAL_SB | VGA_AC_PAL_R | VGA_AC_PAL_G | VGA_AC_PAL_B); + REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_MODE_CONTROL); + REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_MC_GA); + REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_OVERSCAN_COLOR); + REG_WRITE(sc, VGA_AC_WRITE, 0); + REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_COLOR_PLANE_ENABLE); + REG_WRITE(sc, VGA_AC_WRITE, 0x0f); + REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_HORIZ_PIXEL_PANNING); + REG_WRITE(sc, VGA_AC_WRITE, 0); + REG_WRITE(sc, VGA_AC_WRITE, VGA_AC_COLOR_SELECT); + REG_WRITE(sc, VGA_AC_WRITE, 0); + + /* + * Reprogram the graphics controller. + */ + REG_WRITE(sc, VGA_GC_ADDRESS, VGA_GC_SET_RESET); + REG_WRITE(sc, VGA_GC_DATA, 0); + REG_WRITE(sc, VGA_GC_ADDRESS, VGA_GC_ENABLE_SET_RESET); + REG_WRITE(sc, VGA_GC_DATA, 0); + REG_WRITE(sc, VGA_GC_ADDRESS, VGA_GC_COLOR_COMPARE); + REG_WRITE(sc, VGA_GC_DATA, 0); + REG_WRITE(sc, VGA_GC_ADDRESS, VGA_GC_DATA_ROTATE); + REG_WRITE(sc, VGA_GC_DATA, 0); + REG_WRITE(sc, VGA_GC_ADDRESS, VGA_GC_READ_MAP_SELECT); + REG_WRITE(sc, VGA_GC_DATA, 0); + REG_WRITE(sc, VGA_GC_ADDRESS, VGA_GC_MODE); + REG_WRITE(sc, VGA_GC_DATA, 0); + REG_WRITE(sc, VGA_GC_ADDRESS, VGA_GC_MISCELLANEOUS); + REG_WRITE(sc, VGA_GC_DATA, 0x04 + VGA_GC_MISC_GA); + REG_WRITE(sc, VGA_GC_ADDRESS, VGA_GC_COLOR_DONT_CARE); + REG_WRITE(sc, VGA_GC_DATA, 0x0f); + REG_WRITE(sc, VGA_GC_ADDRESS, VGA_GC_BIT_MASK); + REG_WRITE(sc, VGA_GC_DATA, 0xff); + + /* + * Done. Clear the frame buffer. All bit planes are enabled, so + * a single write should clear all planes. + */ + bus_space_set_multi_1(sc->vga_fb.bst, sc->vga_fb.bsh, 0, 0, 65536); - /* Enable the sync signals. */ + /* Re-enable the sync signals. */ REG_WRITE(sc, VGA_CRTC_ADDRESS, VGA_CRTC_MODE_CONTROL); x = REG_READ(sc, VGA_CRTC_DATA); REG_WRITE(sc, VGA_CRTC_DATA, x | VGA_CRTC_MC_HR);
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