Date: Thu, 22 Nov 2012 15:51:59 +0100 From: =?UTF-8?B?xYF1a2FzeiBQxYJhY2hubw==?= <luk@semihalf.com> To: Giovanni Trematerra <gianni@freebsd.org> Cc: freebsd-arm@freebsd.org, cognet@freebsd.org Subject: Re: ARM/SMP, Some patches for review. Message-ID: <50AE3C0F.20809@semihalf.com> In-Reply-To: <CACfq091X6BK7S5jenr46=iwpsyGEz1FdnRLMhXhPdZ4jd06g0w@mail.gmail.com> References: <50AA4E87.3000505@semihalf.com> <CACfq093LakTKEf8E3L5S7QnYcgdnBVpnFSRJo%2BMx=mfgbXpg0g@mail.gmail.com> <50ACE2B4.8010904@semihalf.com> <CACfq091X6BK7S5jenr46=iwpsyGEz1FdnRLMhXhPdZ4jd06g0w@mail.gmail.com>
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On 21.11.2012 17:00, Giovanni Trematerra wrote:
> On Wed, Nov 21, 2012 at 3:18 PM, Łukasz Płachno <luk@semihalf.com> wrote:
>> On 20.11.2012 00:08, Giovanni Trematerra wrote:
>>>
>>> On Mon, Nov 19, 2012 at 4:21 PM, Łukasz Płachno <luk@semihalf.com> wrote:
>>>>
>>>> Hi,
>>>>
>>>> I would like to propose few changes for ARM specific code.
>>>> Three attached patches for freebsd-current allows building SMP-safe world
>>>> for ARM targets and turns on TEX remap for ARMv6 and ARMv7 targets.
>>>>
>>>> More details inside patch files.
>>>>
>>>> Change introduced by "commit-2" removes armv7 targets (armv7 and pj4b)
>>>> from
>>>> kernel.tramp.
>>>> AFAIK this feature is not working properly for armv7 targets and is
>>>> causing
>>>> problem during compilation:
>>>> - LOCORE is defined during kernel compilation but not defined during
>>>> kernel.tramp compilation, so #include pmap.h causes build errors.
>>>>
>>>> I do not think adding hack like this:
>>>> #ifndef LOCORE
>>>> #define LOCORE
>>>> #endif
>>>>
>>>> to allow building something that is already broken is a good idea, so I
>>>> removed cpufunc_asm_pj4b.S and cpufunc_asm_armv7.S from Makefile.arm
>>>
>>>
>>> In commit-2.txt
>>> you should include style changes in sys/arm/arm/cpufunc_asm_armv7.S
>>> into a different patch.
>>
>>
>> fixed
>>
>>
>>>
>>> @@ -63,7 +64,6 @@ FILES_CPU_FUNC = $S/$M/$M/cpufunc_asm_arm7tdmi.S \
>>> $S/$M/$M/cpufunc_asm_xscale.S $S/$M/$M/cpufunc_asm.S \
>>> $S/$M/$M/cpufunc_asm_xscale_c3.S $S/$M/$M/cpufunc_asm_armv5_ec.S
>>> \
>>> $S/$M/$M/cpufunc_asm_fa526.S $S/$M/$M/cpufunc_asm_sheeva.S \
>>> - $S/$M/$M/cpufunc_asm_pj4b.S $S/$M/$M/cpufunc_asm_armv7.S
>>>
>>> You left a trailing back slash but beside that you should clean up
>>> sys/arm/arm/elf_trampoline.c
>>> and not make kernel.tramp to build at all for armv7 cpus or you'll end
>>> up with a linker error
>>> during generation of the kernel.tramp.
>>>
>>
>> Fixed, updated set of patches is attached.
>>
>> - TEX remap is supported only for armv6 (changed to avoid breaking armv6
>> targets)
>> - Fixed issues with build for pre-armv6 targets (tested with make tinderbox
>> TARGETS=arm
>>
>
> 1_SMP_fixes.diff
> You'll endup to get a panic for PandaBoard systems.
> The arm11 functions don't handle the SMP case.
> So I propose to merge the changes below or commit them first.
>
> Index: sys/arm/arm/cpufunc.c
> ===================================================================
> --- sys/arm/arm/cpufunc.c (revision 243182)
> +++ sys/arm/arm/cpufunc.c (working copy)
> @@ -1079,18 +1079,18 @@ struct cpu_functions cortexa_cpufuncs = {
> /* Other functions */
>
> cpufunc_nullop, /* flush_prefetchbuf */
> - arm11_drain_writebuf, /* drain_writebuf */
> + armv7_drain_writebuf, /* drain_writebuf */
> cpufunc_nullop, /* flush_brnchtgt_C */
> (void *)cpufunc_nullop, /* flush_brnchtgt_E */
>
> - arm11_sleep, /* sleep */
> + armv7_cpu_sleep, /* sleep */
>
> /* Soft functions */
>
> cpufunc_null_fixup, /* dataabt_fixup */
> cpufunc_null_fixup, /* prefetchabt_fixup */
>
> - arm11_context_switch, /* context_switch */
> + armv7_context_switch, /* context_switch */
>
> cortexa_setup /* cpu setup */
> };
>
I agree, but with this change I included also:
diff --git a/sys/arm/arm/cpufunc.c b/sys/arm/arm/cpufunc.c
index dd43c27..1d6f93f 100644
--- a/sys/arm/arm/cpufunc.c
+++ b/sys/arm/arm/cpufunc.c
@@ -1049,14 +1049,14 @@ struct cpu_functions cortexa_cpufuncs = {
armv7_tlb_flushID, /* tlb_flushID */
armv7_tlb_flushID_SE, /* tlb_flushID_SE */
- arm11_tlb_flushI, /* tlb_flushI */
- arm11_tlb_flushI_SE, /* tlb_flushI_SE */
- arm11_tlb_flushD, /* tlb_flushD */
- arm11_tlb_flushD_SE, /* tlb_flushD_SE */
+ armv7_tlb_flushID, /* tlb_flushI */
+ armv7_tlb_flushID_SE, /* tlb_flushI_SE */
+ armv7_tlb_flushID, /* tlb_flushD */
+ armv7_tlb_flushID_SE, /* tlb_flushD_SE */
Changes merged into patch 1_SMP_fixes.diff
>
> 2_ARM_cleanup.diff
> Changes to sys/arm/arm/machdep.c don't seem style changes and
> they should live in a separate patch with a different motivation.
>
> I'm not sure changes in sys/arm/arm/locore.S are style ones.
None of changes in this patch are related to style. In this patch I
wanted to improve code readability, not remove style conflicts.
>
> I think that things like this aren't so readable.
> #if (ARM_ARCH_6 + ARM_ARCH_7A) != 0
>
> Instead of things like that wouldn't be better to define different
> macros when the sum is zero or non zero and stick with the
> #if defined/!defined thing?
>
> I mean in sys/arm/arm/cpuconf.h we could make something like this
>
> #if (ARM_ARCH_6 + ARM_ARCH_7A) != 0
> #define ARM_ARCH_6_7A
> #endif
Changed to ARM_ARCH_6_7A
>
> 3_kernel_trampoline.diff
> I think we should not make kernel_trampoline at all for the unsupported CPUs.
> I propose this change to Makefile.arm
>
> Index: sys/conf/Makefile.arm
> ===================================================================
> --- sys/conf/Makefile.arm (revision 243182)
> +++ sys/conf/Makefile.arm (working copy)
> @@ -51,6 +51,7 @@ SYSTEM_LD_TAIL +=;sed s/" + SIZEOF_HEADERS"// ldsc
> ${SYSTEM_LD_}; \
> ${OBJCOPY} -S -O binary ${FULLKERNEL}.noheader \
> ${KERNEL_KO}.bin; \
> + ${NM} ${FULLKERNEL}.noheader | sort > ${FULLKERNEL}.map; \
> rm ${FULLKERNEL}.noheader
>
> .if defined(MFS_IMAGE)
> @@ -62,9 +63,11 @@ FILES_CPU_FUNC = $S/$M/$M/cpufunc_asm_arm7tdmi.S \
> $S/$M/$M/cpufunc_asm_sa1.S $S/$M/$M/cpufunc_asm_arm10.S \
> $S/$M/$M/cpufunc_asm_xscale.S $S/$M/$M/cpufunc_asm.S \
> $S/$M/$M/cpufunc_asm_xscale_c3.S $S/$M/$M/cpufunc_asm_armv5_ec.S \
> $S/$M/$M/cpufunc_asm_fa526.S $S/$M/$M/cpufunc_asm_sheeva.S \
> - $S/$M/$M/cpufunc_asm_pj4b.S $S/$M/$M/cpufunc_asm_armv7.S
> + $S/$M/$M/cpufunc_asm_armv6.S
>
> +NO_TRAMP!= grep 'CPU_CORTEXA\|CPU_MV_PJ4B' opt_global.h || true ; echo
> +
> +.if ${NO_TRAMP} == ""
> KERNEL_EXTRA=trampoline
> KERNEL_EXTRA_INSTALL=kernel.gz.tramp
> trampoline: ${KERNEL_KO}.tramp
> @@ -110,6 +113,7 @@ ${KERNEL_KO}.tramp: ${KERNEL_KO} $S/$M/$M/inckern.
> ${KERNEL_KO}.gz.tramp.bin
> rm ${KERNEL_KO}.tmp.gz ${KERNEL_KO}.tramp.noheader opt_kernname.h \
> inflate-tramp.o tmphack.S
> +.endif
>
> MKMODULESENV+= MACHINE=${MACHINE}
>
Change merged into commit 3.
> 4_tex-remap.diff
> Some style(9) consideration.
> #include(s) should be grouped together in alphabetical order.
> So you should fix the pmap.h includes that you made.
>
#defines reordered
> I'll try to test the pachset ASAP.
>
New set of patches attached.
Regards,
Łukasz Płachno
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commit f54fe0a3d5dd5577eb811a6f3aaef8fdf0d638e9
Author: Lukasz Plachno <luk@semihalf.com>
Date: Thu Nov 22 15:04:32 2012 +0100
arm/smp: Various fixes for enabling SMP operation on ARM systems
- Currently libc is built with ARM SMP support only if specified architecture is one
of the following:
- armv6k
- armv6zk
- armv7
- armv7a
- None of currently available CPUTYPE options allows us to choose one of architectures
above, thus additional target is needed. From now on world for multicore ARM targets
should be built with -CPUTYPE=armv6k or -CPUTYPE=cortexa
- Completely remove option ARM_TP_ADDRESS (no longer used)
- Propagate TLB maintenance operations in SMP mode (follow up for changes proposed
by Giovanni Trematerra)
- pcpup pointer is common for every core, thus using it is not SMP safe
- use proper cpufunctions for cortexa processors
diff --git a/share/mk/bsd.cpu.mk b/share/mk/bsd.cpu.mk
index 747dd29..76d7cfc 100644
--- a/share/mk/bsd.cpu.mk
+++ b/share/mk/bsd.cpu.mk
@@ -98,13 +98,15 @@ _CPUCFLAGS = -march=${CPUTYPE}
. if ${CPUTYPE} == "xscale"
#XXX: gcc doesn't seem to like -mcpu=xscale, and dies while rebuilding itself
#_CPUCFLAGS = -mcpu=xscale
-_CPUCFLAGS = -march=armv5te -D__XSCALE__ -DARM_WANT_TP_ADDRESS
+_CPUCFLAGS = -march=armv5te -D__XSCALE__
. elif ${CPUTYPE} == "armv6"
_CPUCFLAGS = -march=${CPUTYPE} -DARM_ARCH_6=1
+. elif ${CPUTYPE} == "armv6k"
+_CPUCFLAGS = -march=${CPUTYPE} -DARM_ARCH_6=1
. elif ${CPUTYPE} == "cortexa"
-_CPUCFLAGS = -march=armv6 -DARM_ARCH_6=1 -mfpu=vfp
+_CPUCFLAGS = -march=armv6k -DARM_ARCH_6=1 -mfpu=vfp
. else
-_CPUCFLAGS = -mcpu=${CPUTYPE} -DARM_WANT_TP_ADDRESS
+_CPUCFLAGS = -mcpu=${CPUTYPE}
. endif
. elif ${MACHINE_ARCH} == "powerpc"
. if ${CPUTYPE} == "e500"
diff --git a/sys/arm/arm/cpufunc.c b/sys/arm/arm/cpufunc.c
index dd43c27..1d6f93f 100644
--- a/sys/arm/arm/cpufunc.c
+++ b/sys/arm/arm/cpufunc.c
@@ -1049,14 +1049,14 @@ struct cpu_functions cortexa_cpufuncs = {
armv7_tlb_flushID, /* tlb_flushID */
armv7_tlb_flushID_SE, /* tlb_flushID_SE */
- arm11_tlb_flushI, /* tlb_flushI */
- arm11_tlb_flushI_SE, /* tlb_flushI_SE */
- arm11_tlb_flushD, /* tlb_flushD */
- arm11_tlb_flushD_SE, /* tlb_flushD_SE */
+ armv7_tlb_flushID, /* tlb_flushI */
+ armv7_tlb_flushID_SE, /* tlb_flushI_SE */
+ armv7_tlb_flushID, /* tlb_flushD */
+ armv7_tlb_flushID_SE, /* tlb_flushD_SE */
/* Cache operations */
- armv7_idcache_wbinv_all, /* icache_sync_all */
+ armv7_idcache_wbinv_all, /* icache_sync_all */
armv7_icache_sync_range, /* icache_sync_range */
armv7_dcache_wbinv_all, /* dcache_wbinv_all */
@@ -1079,20 +1079,20 @@ struct cpu_functions cortexa_cpufuncs = {
/* Other functions */
cpufunc_nullop, /* flush_prefetchbuf */
- arm11_drain_writebuf, /* drain_writebuf */
+ armv7_drain_writebuf, /* drain_writebuf */
cpufunc_nullop, /* flush_brnchtgt_C */
(void *)cpufunc_nullop, /* flush_brnchtgt_E */
- arm11_sleep, /* sleep */
+ armv7_cpu_sleep, /* sleep */
/* Soft functions */
cpufunc_null_fixup, /* dataabt_fixup */
cpufunc_null_fixup, /* prefetchabt_fixup */
- arm11_context_switch, /* context_switch */
+ armv7_context_switch, /* context_switch */
- cortexa_setup /* cpu setup */
+ cortexa_setup /* cpu setup */
};
#endif /* CPU_CORTEXA */
diff --git a/sys/arm/arm/locore.S b/sys/arm/arm/locore.S
index e81912c..99b214a 100644
--- a/sys/arm/arm/locore.S
+++ b/sys/arm/arm/locore.S
@@ -166,7 +166,11 @@ Lunmapped:
orr r0, r0, #2 /* Set TTB shared memory flag */
#endif
mcr p15, 0, r0, c2, c0, 0 /* Set TTB */
- mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
+#ifdef SMP
+ mcr p15, 0, r0, c8, c3, 0 /* Invalidate I+D TLBs Inner Shareable */
+#else
+ mcr p15, 0, r0, c8, c7, 0 /* Invalidate I+D TLBs */
+#endif
#if defined(CPU_ARM11) || defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B)
mov r0, #0
@@ -361,7 +365,11 @@ Ltag:
orr r0, r0, #0 /* Set TTB shared memory flag */
#endif
mcr p15, 0, r0, c2, c0, 0 /* Set TTB */
- mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
+#ifdef SMP
+ mcr p15, 0, r0, c8, c3, 0 /* Invalidate I+D TLBs Inner Shareable */
+#else
+ mcr p15, 0, r0, c8, c7, 0 /* Invalidate I+D TLBs */
+#endif
#if defined(CPU_ARM11) || defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA)
mov r0, #0
diff --git a/sys/arm/include/pcpu.h b/sys/arm/include/pcpu.h
index f12f903..43ffb44 100644
--- a/sys/arm/include/pcpu.h
+++ b/sys/arm/include/pcpu.h
@@ -100,8 +100,8 @@ set_tls(void *tls)
#define PCPU_GET(member) (get_pcpu()->pc_ ## member)
#define PCPU_ADD(member, value) (get_pcpu()->pc_ ## member += (value))
#define PCPU_INC(member) PCPU_ADD(member, 1)
-#define PCPU_PTR(member) (&pcpup->pc_ ## member)
-#define PCPU_SET(member,value) (pcpup->pc_ ## member = (value))
+#define PCPU_PTR(member) (&get_pcpu()->pc_ ## member)
+#define PCPU_SET(member,value) (get_pcpu()->pc_ ## member = (value))
void pcpu0_init(void);
#endif /* _KERNEL */
diff --git a/sys/conf/options.arm b/sys/conf/options.arm
index 2fe7b9f..e9c8187 100644
--- a/sys/conf/options.arm
+++ b/sys/conf/options.arm
@@ -7,7 +7,6 @@ ARM_L2_PIPT opt_global.h
ARM_MANY_BOARD opt_global.h
ARM_USE_SMALL_ALLOC opt_global.h
ARM_VFP_SUPPORT opt_global.h
-ARM_WANT_TP_ADDRESS opt_global.h
COUNTS_PER_SEC opt_timer.h
CPU_ARM9 opt_global.h
CPU_ARM9E opt_global.h
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commit 3ad13773d26bffe4212858c38280d1bb874548e6
Author: Lukasz Plachno <luk@semihalf.com>
Date: Thu Nov 22 09:41:09 2012 +0100
arm: Cleanup in ARM specific code
- Unify descriptions for cache and TLB maintenance operations
- Use architecture macros instead of CPU specific ones in generic code
diff --git a/sys/arm/arm/cpufunc_asm_armv7.S b/sys/arm/arm/cpufunc_asm_armv7.S
index 58f295c..03561b8 100644
--- a/sys/arm/arm/cpufunc_asm_armv7.S
+++ b/sys/arm/arm/cpufunc_asm_armv7.S
@@ -71,9 +71,9 @@ ENTRY(armv7_setttb)
orr r0, r0, #PT_ATTR
mcr p15, 0, r0, c2, c0, 0 /* Translation Table Base Register 0 (TTBR0) */
#ifdef SMP
- mcr p15, 0, r0, c8, c3, 0 /* invalidate I+D TLBs Inner Shareable*/
+ mcr p15, 0, r0, c8, c3, 0 /* Invalidate I+D TLBs Inner Shareable */
#else
- mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
+ mcr p15, 0, r0, c8, c7, 0 /* Invalidate I+D TLBs */
#endif
dsb
isb
@@ -82,11 +82,11 @@ ENTRY(armv7_setttb)
ENTRY(armv7_tlb_flushID)
dsb
#ifdef SMP
- mcr p15, 0, r0, c8, c3, 0 /* flush I+D tlb */
- mcr p15, 0, r0, c7, c1, 6 /* flush BTB */
+ mcr p15, 0, r0, c8, c3, 0 /* Invalidate I+D TLBs Inner Shareable */
+ mcr p15, 0, r0, c7, c1, 6 /* Flush BTB Inner Shareable */
#else
- mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
- mcr p15, 0, r0, c7, c5, 6 /* flush BTB */
+ mcr p15, 0, r0, c8, c7, 0 /* Invalidate I+D TLBs */
+ mcr p15, 0, r0, c7, c5, 6 /* Flush BTB */
#endif
dsb
isb
@@ -96,10 +96,10 @@ ENTRY(armv7_tlb_flushID_SE)
ldr r1, .Lpage_mask
bic r0, r0, r1
#ifdef SMP
- mcr p15, 0, r0, c8, c3, 1 /* flush D tlb single entry Inner Shareable*/
+ mcr p15, 0, r0, c8, c3, 1 /* Invalidate I+D TLB single entry Inner Shareable */
mcr p15, 0, r0, c7, c1, 6 /* flush BTB Inner Shareable */
#else
- mcr p15, 0, r0, c8, c7, 1 /* flush D tlb single entry */
+ mcr p15, 0, r0, c8, c7, 1 /* Invalidate I+D TLB single entry Inner Shareable */
mcr p15, 0, r0, c7, c5, 6 /* flush BTB */
#endif
dsb
@@ -262,9 +262,9 @@ ENTRY(armv7_context_switch)
mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */
#ifdef SMP
- mcr p15, 0, r0, c8, c3, 0 /* and flush the I+D tlbs Inner Sharable */
+ mcr p15, 0, r0, c8, c3, 0 /* Invalidate I+D TLBs Inner Shareable */
#else
- mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */
+ mcr p15, 0, r0, c8, c7, 0 /* Invalidate I+D TLBs */
#endif
dsb
isb
diff --git a/sys/arm/arm/locore.S b/sys/arm/arm/locore.S
index 99b214a..e6349e6 100644
--- a/sys/arm/arm/locore.S
+++ b/sys/arm/arm/locore.S
@@ -38,6 +38,7 @@
#include <machine/asm.h>
#include <machine/armreg.h>
#include <machine/pte.h>
+#include <machine/pmap.h>
__FBSDID("$FreeBSD$");
@@ -172,7 +173,7 @@ Lunmapped:
mcr p15, 0, r0, c8, c7, 0 /* Invalidate I+D TLBs */
#endif
-#if defined(CPU_ARM11) || defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B)
+#if defined(ARM_ARCH_6_7A)
mov r0, #0
mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */
#endif
@@ -182,7 +183,7 @@ Lunmapped:
mcr p15, 0, r0, c3, c0, 0
/* Enable MMU */
mrc p15, 0, r0, c1, c0, 0
-#if defined(CPU_ARM11) || defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B)
+#if defined(ARM_ARCH_6_7A)
orr r0, r0, #CPU_CONTROL_V6_EXTPAGE
#endif
orr r0, r0, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE)
@@ -371,7 +372,7 @@ Ltag:
mcr p15, 0, r0, c8, c7, 0 /* Invalidate I+D TLBs */
#endif
-#if defined(CPU_ARM11) || defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA)
+#if defined(ARM_ARCH_6_7A)
mov r0, #0
mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */
#endif
@@ -383,7 +384,7 @@ Ltag:
mcr p15, 0, r0, c3, c0, 0
/* Enable MMU */
mrc p15, 0, r0, c1, c0, 0
-#if defined(CPU_ARM11) || defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA)
+#if defined(ARM_ARCH_6_7A)
orr r0, r0, #CPU_CONTROL_V6_EXTPAGE
#endif
orr r0, r0, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE)
diff --git a/sys/arm/arm/machdep.c b/sys/arm/arm/machdep.c
index 17a60c2..7ebbbb0 100644
--- a/sys/arm/arm/machdep.c
+++ b/sys/arm/arm/machdep.c
@@ -834,7 +834,7 @@ fake_preload_metadata(struct arm_boot_params *abp __unused)
void
pcpu0_init(void)
{
-#if ARM_ARCH_6 || ARM_ARCH_7A || defined(CPU_MV_PJ4B)
+#if defined(ARM_ARCH_6_7A)
set_pcpu(pcpup);
#endif
pcpu_init(pcpup, 0, sizeof(struct pcpu));
diff --git a/sys/arm/include/cpuconf.h b/sys/arm/include/cpuconf.h
index 95d4b91..18954b3 100644
--- a/sys/arm/include/cpuconf.h
+++ b/sys/arm/include/cpuconf.h
@@ -102,6 +102,10 @@
#define ARM_ARCH_7A 0
#endif
+#if ARM_ARCH_6 || ARM_ARCH_7A
+#define ARM_ARCH_6_7A
+#endif
+
#define ARM_NARCH (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 | ARM_ARCH_7A)
#if ARM_NARCH == 0 && !defined(KLD_MODULE) && defined(_KERNEL)
#error ARM_NARCH is 0
diff --git a/sys/arm/include/pcpu.h b/sys/arm/include/pcpu.h
index 43ffb44..3626014 100644
--- a/sys/arm/include/pcpu.h
+++ b/sys/arm/include/pcpu.h
@@ -60,7 +60,7 @@ struct pcb;
struct pcpu;
extern struct pcpu *pcpup;
-#if ARM_ARCH_6 || ARM_ARCH_7A
+#if defined(ARM_ARCH_6_7A)
/* or ARM_TP_ADDRESS mark REMOVE ME NOTE */
static inline struct pcpu *
get_pcpu(void)
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commit 429593cf4808f288aeb171e8ce6863f3cd23358b
Author: Lukasz Plachno <luk@semihalf.com>
Date: Thu Nov 22 10:05:16 2012 +0100
arm: Remove armv7 targets from kernel.trampoline
- armv7 targets are not working currently
- add debug kernel map for build targets
- disable building kernel trampoline for not supported targets
diff --git a/sys/arm/arm/elf_trampoline.c b/sys/arm/arm/elf_trampoline.c
index 2a218bf..c47afa6 100644
--- a/sys/arm/arm/elf_trampoline.c
+++ b/sys/arm/arm/elf_trampoline.c
@@ -74,26 +74,18 @@ void __startC(void);
#define cpu_idcache_wbinv_all xscale_cache_purgeID
#elif defined(CPU_XSCALE_81342)
#define cpu_idcache_wbinv_all xscalec3_cache_purgeID
-#elif defined(CPU_MV_PJ4B)
-#if !defined(SOC_MV_ARMADAXP)
-#define cpu_idcache_wbinv_all armv6_idcache_wbinv_all
#else
-#define cpu_idcache_wbinv_all() armadaxp_idcache_wbinv_all
+#define cpu_idcache_wbinv_all()
#endif
-#endif /* CPU_MV_PJ4B */
+
#ifdef CPU_XSCALE_81342
#define cpu_l2cache_wbinv_all xscalec3_l2cache_purge
#elif defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY)
#define cpu_l2cache_wbinv_all sheeva_l2cache_wbinv_all
-#elif defined(CPU_CORTEXA)
-#define cpu_idcache_wbinv_all armv7_idcache_wbinv_all
-#define cpu_l2cache_wbinv_all()
#else
-#define cpu_l2cache_wbinv_all()
+#define cpu_l2cache_wbinv_all()
#endif
-static void armadaxp_idcache_wbinv_all(void);
-
int arm_picache_size;
int arm_picache_line_size;
int arm_picache_ways;
@@ -354,18 +346,6 @@ arm9_setup(void)
arm9_dcache_index_max = 0U - arm9_dcache_index_inc;
}
-static void
-armadaxp_idcache_wbinv_all(void)
-{
- uint32_t feat;
-
- __asm __volatile("mrc p15, 0, %0, c0, c1, 0" : "=r" (feat));
- if (feat & ARM_PFR0_THUMBEE_MASK)
- armv7_idcache_wbinv_all();
- else
- armv6_idcache_wbinv_all();
-
-}
#ifdef KZIP
static unsigned char *orig_input, *i_input, *i_output;
diff --git a/sys/conf/Makefile.arm b/sys/conf/Makefile.arm
index 6270aef..78c7b32 100644
--- a/sys/conf/Makefile.arm
+++ b/sys/conf/Makefile.arm
@@ -51,6 +51,7 @@ SYSTEM_LD_TAIL +=;sed s/" + SIZEOF_HEADERS"// ldscript.$M\
${SYSTEM_LD_}; \
${OBJCOPY} -S -O binary ${FULLKERNEL}.noheader \
${KERNEL_KO}.bin; \
+ ${NM} ${FULLKERNEL}.noheader | sort > ${FULLKERNEL}.map; \
rm ${FULLKERNEL}.noheader
.if defined(MFS_IMAGE)
@@ -63,8 +64,11 @@ FILES_CPU_FUNC = $S/$M/$M/cpufunc_asm_arm7tdmi.S \
$S/$M/$M/cpufunc_asm_xscale.S $S/$M/$M/cpufunc_asm.S \
$S/$M/$M/cpufunc_asm_xscale_c3.S $S/$M/$M/cpufunc_asm_armv5_ec.S \
$S/$M/$M/cpufunc_asm_fa526.S $S/$M/$M/cpufunc_asm_sheeva.S \
- $S/$M/$M/cpufunc_asm_pj4b.S $S/$M/$M/cpufunc_asm_armv7.S
+ $S/$M/$M/cpufunc_asm_armv6.S
+NO_TRAMP!= grep 'CPU_CORTEXA\|CPU_MV_PJ4B' opt_global.h || true ; echo
+
+.if ${NO_TRAMP} == ""
KERNEL_EXTRA=trampoline
KERNEL_EXTRA_INSTALL=kernel.gz.tramp
trampoline: ${KERNEL_KO}.tramp
@@ -110,6 +114,7 @@ ${KERNEL_KO}.tramp: ${KERNEL_KO} $S/$M/$M/inckern.S $S/$M/$M/elf_trampoline.c
${KERNEL_KO}.gz.tramp.bin
rm ${KERNEL_KO}.tmp.gz ${KERNEL_KO}.tramp.noheader opt_kernname.h \
inflate-tramp.o tmphack.S
+.endif
MKMODULESENV+= MACHINE=${MACHINE}
--------------090609080402090500000504
Content-Type: text/x-patch;
name="4_tex_remap.diff"
Content-Transfer-Encoding: 7bit
Content-Disposition: attachment;
filename="4_tex_remap.diff"
commit dc9a9b9e970d51a28ceaf71d3d0cf24f69375329
Author: Lukasz Plachno <luk@semihalf.com>
Date: Thu Nov 22 09:57:32 2012 +0100
arm: Implement new way for pagetable memory attributes management
- initialize PRRR and NMRR registers in cp15
- enable TEX remapping
- create macros for TTB attributes
diff --git a/sys/arm/arm/cpufunc.c b/sys/arm/arm/cpufunc.c
index 1d6f93f..c35becc 100644
--- a/sys/arm/arm/cpufunc.c
+++ b/sys/arm/arm/cpufunc.c
@@ -2327,6 +2327,7 @@ pj4bv6_setup(char *args)
cpuctrl |= CPU_CONTROL_VECRELOC;
cpuctrl |= (0x5 << 16);
cpuctrl |= CPU_CONTROL_V6_EXTPAGE;
+ cpuctrl |= CPU_CONTROL_TEX_REMAP;
/* XXX not yet */
/* cpuctrl |= CPU_CONTROL_L2_ENABLE; */
@@ -2362,6 +2363,7 @@ pj4bv7_setup(args)
cpuctrl |= CPU_CONTROL_VECRELOC;
cpuctrl |= (0x5 << 16) | (1 < 22);
cpuctrl |= CPU_CONTROL_V6_EXTPAGE;
+ cpuctrl |= CPU_CONTROL_TEX_REMAP;
/* Clear out the cache */
cpu_idcache_wbinv_all();
@@ -2392,7 +2394,8 @@ cortexa_setup(char *args)
cpuctrl = CPU_CONTROL_MMU_ENABLE |
CPU_CONTROL_IC_ENABLE |
CPU_CONTROL_DC_ENABLE |
- CPU_CONTROL_BPRD_ENABLE;
+ CPU_CONTROL_BPRD_ENABLE |
+ CPU_CONTROL_TEX_REMAP;
#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
diff --git a/sys/arm/arm/cpufunc_asm_armv7.S b/sys/arm/arm/cpufunc_asm_armv7.S
index 03561b8..d6f9d59 100644
--- a/sys/arm/arm/cpufunc_asm_armv7.S
+++ b/sys/arm/arm/cpufunc_asm_armv7.S
@@ -32,6 +32,8 @@
#include <machine/asm.h>
__FBSDID("$FreeBSD$");
+#include <machine/pmap.h>
+
.cpu cortex-a8
.Lcoherency_level:
@@ -45,30 +47,13 @@ __FBSDID("$FreeBSD$");
.Lpage_mask:
.word 0xfff
-#define PT_NOS (1 << 5)
-#define PT_S (1 << 1)
-#define PT_INNER_NC 0
-#define PT_INNER_WT (1 << 0)
-#define PT_INNER_WB ((1 << 0) | (1 << 6))
-#define PT_INNER_WBWA (1 << 6)
-#define PT_OUTER_NC 0
-#define PT_OUTER_WT (2 << 3)
-#define PT_OUTER_WB (3 << 3)
-#define PT_OUTER_WBWA (1 << 3)
-
-#ifdef SMP
-#define PT_ATTR (PT_S|PT_INNER_WT|PT_OUTER_WT|PT_NOS)
-#else
-#define PT_ATTR (PT_INNER_WT|PT_OUTER_WT)
-#endif
-
ENTRY(armv7_setttb)
stmdb sp!, {r0, lr}
bl _C_LABEL(armv7_idcache_wbinv_all) /* clean the D cache */
ldmia sp!, {r0, lr}
dsb
- orr r0, r0, #PT_ATTR
+ orr r0, r0, #TTB_ATTR
mcr p15, 0, r0, c2, c0, 0 /* Translation Table Base Register 0 (TTBR0) */
#ifdef SMP
mcr p15, 0, r0, c8, c3, 0 /* Invalidate I+D TLBs Inner Shareable */
@@ -258,7 +243,7 @@ ENTRY(armv7_cpu_sleep)
ENTRY(armv7_context_switch)
dsb
- orr r0, r0, #PT_ATTR
+ orr r0, r0, #TTB_ATTR
mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */
#ifdef SMP
diff --git a/sys/arm/arm/cpufunc_asm_pj4b.S b/sys/arm/arm/cpufunc_asm_pj4b.S
index f6890d9..f2eba94 100644
--- a/sys/arm/arm/cpufunc_asm_pj4b.S
+++ b/sys/arm/arm/cpufunc_asm_pj4b.S
@@ -33,6 +33,7 @@
__FBSDID("$FreeBSD$");
#include <machine/param.h>
+#include <machine/pmap.h>
.Lpj4b_cache_line_size:
.word _C_LABEL(arm_pdcache_line_size)
@@ -40,9 +41,7 @@ __FBSDID("$FreeBSD$");
ENTRY(pj4b_setttb)
/* Cache synchronization is not required as this core has PIPT caches */
mcr p15, 0, r1, c7, c10, 4 /* drain the write buffer */
-#ifdef SMP
- orr r0, r0, #2 /* Set TTB shared memory flag */
-#endif
+ orr r0, r0, #TTB_ATTR /* Set TTB memory flags */
mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
RET
@@ -199,4 +198,5 @@ ENTRY(pj4b_config)
orr r0, r0, #(1 << 5)
mcr p15, 0, r0, c1, c0, 1
#endif
+
RET
diff --git a/sys/arm/arm/locore.S b/sys/arm/arm/locore.S
index e6349e6..88a85ac 100644
--- a/sys/arm/arm/locore.S
+++ b/sys/arm/arm/locore.S
@@ -163,8 +163,9 @@ Lunmapped:
orrne r5, r5, #PHYSADDR
movne pc, r5
-#if defined(SMP)
- orr r0, r0, #2 /* Set TTB shared memory flag */
+#if ARM_MMU_V7 != 0
+ /* For primary pagetable normal non-cacheable memory is used */
+ orr r0, r0, #TTB_FLAGS_2 /* Set TTB memory flags */
#endif
mcr p15, 0, r0, c2, c0, 0 /* Set TTB */
#ifdef SMP
@@ -173,6 +174,19 @@ Lunmapped:
mcr p15, 0, r0, c8, c7, 0 /* Invalidate I+D TLBs */
#endif
+#if ARM_MMU_V7 != 0
+ /* Set PRRR and NMRR cp15 registers */
+ ldr r0, =PRRR
+ mcr p15, 0, r0, c10, c2, 0
+ ldr r0, =NMRR
+ mcr p15, 0, r0, c10, c2, 1
+
+ /* Set TEX Remap */
+ mrc p15, 0, r0, c1, c0, 0
+ orr r0, #CPU_CONTROL_TEX_REMAP
+ mcr p15, 0, r0, c1, c0, 0
+#endif
+
#if defined(ARM_ARCH_6_7A)
mov r0, #0
mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */
@@ -362,8 +376,10 @@ Ltag:
bic r0, r0, #0xf0000000
orr r0, r0, #PHYSADDR
ldr r0, [r0]
-#if defined(SMP)
- orr r0, r0, #0 /* Set TTB shared memory flag */
+
+#if ARM_MMU_V7 != 0
+ /* For primary pagetable normal non-cacheable memory is used */
+ orr r0, r0, #TTB_FLAGS_2 /* Set TTB memory flags */
#endif
mcr p15, 0, r0, c2, c0, 0 /* Set TTB */
#ifdef SMP
@@ -372,6 +388,19 @@ Ltag:
mcr p15, 0, r0, c8, c7, 0 /* Invalidate I+D TLBs */
#endif
+#if ARM_MMU_V7 != 0
+ /* Set PRRR and NMRR cp15 registers */
+ ldr r0, =PRRR
+ mcr p15, 0, r0, c10, c2, 0
+ ldr r0, =NMRR
+ mcr p15, 0, r0, c10, c2, 1
+
+ /* Set TEX Remap */
+ mrc p15, 0, r0, c1, c0, 0
+ orr r0, #CPU_CONTROL_TEX_REMAP
+ mcr p15, 0, r0, c1, c0, 0
+#endif
+
#if defined(ARM_ARCH_6_7A)
mov r0, #0
mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */
diff --git a/sys/arm/arm/pmap-v6.c b/sys/arm/arm/pmap-v6.c
index a44bdbf..aafb1e4 100644
--- a/sys/arm/arm/pmap-v6.c
+++ b/sys/arm/arm/pmap-v6.c
@@ -386,6 +386,48 @@ static struct vm_object pvzone_obj;
static int pv_entry_count=0, pv_entry_max=0, pv_entry_high_water=0;
static struct rwlock pvh_global_lock;
+#if defined(SMP)
+#define L1_SHAREABLE L1_SHARED
+#define L2_SHAREABLE L2_SHARED
+#else
+#define L1_SHAREABLE 0
+#define L2_SHAREABLE 0
+#endif /* SMP */
+
+#if ARM_MMU_V7 != 0
+int l1_mem_types[] = {
+ (L1_SHAREABLE),
+ (L1_SHAREABLE | L1_S_B),
+ (L1_SHAREABLE | L1_S_C),
+ (L1_SHAREABLE | L1_S_C | L1_S_B),
+ (L1_SHAREABLE | L1_S_TEX(1)),
+ (L1_SHAREABLE | L1_S_TEX(1) | L1_S_B),
+ (L1_SHAREABLE),
+ (L1_SHAREABLE | L1_S_TEX(1) | L1_S_C | L1_S_B)
+};
+
+int l2l_mem_types[] = {
+ (L2_SHAREABLE),
+ (L2_SHAREABLE | L2_B),
+ (L2_SHAREABLE | L2_C),
+ (L2_SHAREABLE | L2_C | L2_B),
+ (L2_SHAREABLE | L2_L_TEX(1)),
+ (L2_SHAREABLE | L2_L_TEX(1) | L2_B),
+ (L2_SHAREABLE),
+ (L2_SHAREABLE | L2_L_TEX(1) | L2_C | L2_B)
+};
+
+int l2s_mem_types[] = {
+ (L2_SHAREABLE),
+ (L2_SHAREABLE | L2_B),
+ (L2_SHAREABLE | L2_C),
+ (L2_SHAREABLE | L2_C | L2_B),
+ (L2_SHAREABLE | L2_S_TEX(1)),
+ (L2_SHAREABLE | L2_S_TEX(1) | L2_B),
+ (L2_SHAREABLE),
+ (L2_SHAREABLE | L2_S_TEX(1) | L2_C | L2_B)
+};
+#else
int l1_mem_types[] = {
ARM_L1S_STRONG_ORD,
ARM_L1S_DEVICE_NOSHARE,
@@ -415,6 +457,7 @@ int l2s_mem_types[] = {
ARM_L2S_NRML_IWB_OWB,
ARM_L2S_NRML_IWBA_OWBA
};
+#endif
/*
* This list exists for the benefit of pmap_map_chunk(). It keeps track
diff --git a/sys/arm/include/armreg.h b/sys/arm/include/armreg.h
index 05b3846..f5ccfb9 100644
--- a/sys/arm/include/armreg.h
+++ b/sys/arm/include/armreg.h
@@ -286,6 +286,7 @@
#define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */
#define CPU_CONTROL_V6_EXTPAGE 0x00800000 /* XP: ARMv6 extended page tables */
#define CPU_CONTROL_L2_ENABLE 0x04000000 /* L2 Cache enabled */
+#define CPU_CONTROL_TEX_REMAP 0x10000000 /* TEX Remap enabled */
#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE
diff --git a/sys/arm/include/pmap.h b/sys/arm/include/pmap.h
index e20bf18..b46e3b1 100644
--- a/sys/arm/include/pmap.h
+++ b/sys/arm/include/pmap.h
@@ -52,33 +52,140 @@
#include <machine/pte.h>
#include <machine/cpuconf.h>
+
+/*
+ * When TEX remap is enabled (SCTLR.TRE is set to 1),
+ * PRRR and NMRR values needs to be initialized before MMU is used.
+ *
+ * TEX[0],C,B -> index(n)
+ *
+ * PMRR -> memory type (strongly ordered, device, normal), shareability
+ * TR (PRRR[2n+1:2n]) -> memory type
+ * NOS (PRRR[24+n]) -> non outer shareable attribute
+ * DS0 (PRRR[16]) -> device memory shareable attribute (S = 0)
+ * DS1 (PRRR[17]) -> device memory shareable attribute (S = 1)
+ * NS0 (PRRR[18]) -> normal memory shareable attribute (S = 0)
+ * NS1 (PRRR[19]) -> normal memory shareable attribute (S = 1)
+ *
+ * NMRR -> cache policy (no cache, WT, WB, WBWA)
+ * IR (NMRR[2n+1;2n]) -> inner cache property
+ * OR (NMRR[2n+17;2n+16]) -> outer cache property
+ *
+ * Memory type index TR IR OR
+ * STRONGLY_ORDERED 0 00
+ * DEVICE 1 01
+ * NOCACHE 2 10 00 00
+ * IWT_OWT 3 10 10 10
+ * IWB_OWB 4 10 11 11
+ * IWBA_OWBA 5 10 01 01
+ * RESERVED 6
+ * IWBA_OWB 7 10 01 11
+ *
+ * Other attributes:
+ * DS0 = 0
+ * DS1 = 1
+ * NS0 = 0
+ * NS1 = 1
+ *
+ * Outer shareability is implementation dependent feature in armv7
+ * specification, for now safe value (disable outer shareability) is used
+ * NOS[0:7] = 1
+ */
+
+#define NMRR 0xc7804780
+#define PRRR 0xff0a8aa4
+
+/*
+ * ARMv7 TTBR bit definition
+ */
+#if ARM_MMU_V7 != 0
+#define PT_NOS (1 << 5)
+#define PT_OUTER_NC 0
+#define PT_OUTER_WB (3 << 3)
+#define PT_OUTER_WBWA (1 << 3)
+#define PT_OUTER_WT (2 << 3)
+#define PT_S (1 << 1)
+#if defined(SMP)
+#define PT_INNER_NC 0
+#define PT_INNER_WB ((1 << 0) | (1 << 6))
+#define PT_INNER_WBWA (1 << 6)
+#define PT_INNER_WT (1 << 0)
+#define PT_SHAREABLE (PT_S)
+#else
+
+/*
+ * In ARMv6 and ARMV7 without multiprocessor extension,
+ * pagetable memory inner cacheability policy is implementation defined
+ */
+#define PT_INNER_NC 0
+#define PT_INNER_WB (1 << 0)
+#define PT_INNER_WBWA (1 << 0)
+#define PT_INNER_WT (1 << 0)
+#define PT_SHAREABLE 0
+#endif /* SMP */
+
+#define TTB_FLAGS_0 (PT_SHAREABLE | PT_NOS | PT_INNER_NC | PT_OUTER_NC)
+#define TTB_FLAGS_1 (PT_SHAREABLE | PT_NOS | PT_INNER_NC | PT_OUTER_NC)
+#define TTB_FLAGS_2 (PT_SHAREABLE | PT_NOS | PT_INNER_NC | PT_OUTER_NC)
+#define TTB_FLAGS_3 (PT_SHAREABLE | PT_NOS | PT_INNER_WT | PT_OUTER_WT)
+#define TTB_FLAGS_4 (PT_SHAREABLE | PT_NOS | PT_INNER_WB | PT_OUTER_WB)
+#define TTB_FLAGS_5 (PT_SHAREABLE | PT_NOS | PT_INNER_WBWA | PT_OUTER_WBWA)
+#define TTB_FLAGS_6 (PT_SHAREABLE | PT_NOS | PT_INNER_NC | PT_OUTER_NC)
+#define TTB_FLAGS_7 (PT_SHAREABLE | PT_NOS | PT_INNER_WBWA | PT_OUTER_WB)
+#endif /* (ARM_MMU_V7) != 0 */
+
/*
- * Pte related macros
+ * Pte related macros
+ *
+ * Memory types when tex remap is enabled (armv6 and armv7):
+ * 0 - strongly ordered
+ * 1 - device memory,
+ * 2 - normal memory, non cacheable
+ * 3 - normal memory, inner write-through, outer write-through
+ * 4 - normal memory, inner write-back, outer write-back
+ * 5 - normal memory, inner write-back write-allocate,
+ * outer write-back write-allocate
+ * 6 - reserved value
+ * 7 - normal memory, inner write-back write-allocate, outer write-back
+ *
+ * Memory types when tex remap is disabled / not supported:
+ * 0 - strongly ordered
+ * 1 - device memory, non shareable
+ * 2 - device memory, shareable
+ * 3 - normal memory, non cacheable
+ * 4 - normal memory, inner write-through, outer write-through
+ * 5 - normal memory, inner write-back, outer write-back
+ * 6 - normal memory, inner write-back write-allocate,
+ * outer write-back write-allocate
*/
-#if ARM_ARCH_6 || ARM_ARCH_7A
+
+#if ARM_MMU_V7 != 0
+#define PTE_CACHE 5
+#define PTE_DEVICE 1
+#define PTE_NOCACHE 2
+
+/* TTB_FLAGS number must be the same as PTE_PAGETABLE value */
+#define PTE_PAGETABLE 5
+#define TTB_ATTR TTB_FLAGS_5
+#elif ARM_MMU_V6 != 0
#ifdef SMP
#define PTE_NOCACHE 2
#else
#define PTE_NOCACHE 1
-#endif
+#endif /* SMP */
#define PTE_CACHE 4
#define PTE_DEVICE 2
#define PTE_PAGETABLE 4
-#else
-#define PTE_NOCACHE 1
+
+#define TTB_ATTR 0
+#else /* ARM_MMU_V6 == 0 && ARM_MMU_V7 == 0 */
#define PTE_CACHE 2
+#define PTE_NOCACHE 1
#define PTE_PAGETABLE 3
+
+#define TTB_ATTR 0
#endif
-enum mem_type {
- STRONG_ORD = 0,
- DEVICE_NOSHARE,
- DEVICE_SHARE,
- NRML_NOCACHE,
- NRML_IWT_OWT,
- NRML_IWB_OWB,
- NRML_IWBA_OWBA
-};
#ifndef LOCORE
@@ -427,6 +534,8 @@ extern int pmap_needs_pte_sync;
#elif defined(CPU_XSCALE_81342)
#define PMAP_NEEDS_PTE_SYNC 1
#define PMAP_INCLUDE_PTE_SYNC
+#elif ARM_MMU_V7 != 0
+#define PMAP_NEEDS_PTE_SYNC 1
#elif (ARM_MMU_SA1 == 0)
#define PMAP_NEEDS_PTE_SYNC 0
#endif
--------------090609080402090500000504
Content-Type: text/x-patch;
name="5_memory_barriers.diff"
Content-Transfer-Encoding: 7bit
Content-Disposition: attachment;
filename="5_memory_barriers.diff"
commit 03e3d3e90ddaa03c6a62265b96b55f122a8abb48
Author: Lukasz Plachno <luk@semihalf.com>
Date: Tue Nov 20 09:21:03 2012 +0100
arm: Add macros for memory barriers
- In armv6 "dsb" operation is not supported
- In armv7 use of register r7 in cp15 is deprecated
diff --git a/sys/arm/include/atomic.h b/sys/arm/include/atomic.h
index 1a96176..2050b55 100644
--- a/sys/arm/include/atomic.h
+++ b/sys/arm/include/atomic.h
@@ -47,9 +47,35 @@
#include <machine/cpuconf.h>
#endif
-#define mb()
-#define wmb()
-#define rmb()
+#if ARM_ARCH_7A != 0
+#define mb() do { \
+ __asm __volatile("dsb"); \
+ } while (0)
+#define wmb() do { \
+ __asm __volatile("dsb"); \
+ } while (0)
+#define rmb() do { \
+ __asm __volatile("dsb"); \
+ } while (0)
+#elif ARM_ARCH_6 != 0
+#define mb() do { \
+ uint32_t reg = 0; \
+ __asm __volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (reg)); \
+ } while (0)
+#define wmb() do { \
+ uint32_t reg = 0; \
+ __asm __volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (reg)); \
+ } while (0)
+#define rmb() do { \
+ uint32_t reg = 0; \
+ __asm __volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (reg)); \
+ } while (0)
+#else
+#define mb()
+#define wmb()
+#define rmb()
+#endif
+
#ifndef I32_bit
#define I32_bit (1 << 7) /* IRQ disable */
--------------090609080402090500000504--
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