Date: Sat, 3 Oct 2015 10:02:56 +0300 From: Konstantin Belousov <kostikbel@gmail.com> To: Ian Lepore <ian@freebsd.org> Cc: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org, gjb@freebsd.org Subject: Re: svn commit: r288492 - head/sys/arm/arm Message-ID: <20151003070256.GD11284@kib.kiev.ua> In-Reply-To: <1443803276.66572.72.camel@freebsd.org> References: <201510021326.t92DQ0Ds002986@repo.freebsd.org> <1443795970.66572.68.camel@freebsd.org> <20151002152059.GY11284@kib.kiev.ua> <1443803276.66572.72.camel@freebsd.org>
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On Fri, Oct 02, 2015 at 10:27:56AM -0600, Ian Lepore wrote: > On Fri, 2015-10-02 at 18:20 +0300, Konstantin Belousov wrote: > > On Fri, Oct 02, 2015 at 08:26:10AM -0600, Ian Lepore wrote: > > > Some arm documentation refers to the need for "support code" when the > > > flush-to-zero option is disabled on VFPv2 hardware (which for us would > > > be just the RPi I think). Do we have that support code? What happens > > > if it's missing? I can't actually find any info on exactly what that > > > support code is supposed to do. For all I know, we have the required > > > code in libm. Or maybe what's needed is exception-handling code in the > > > kernel. I can't find any info on what they mean by "support code" in > > > this context. > > The fpscr register is user-modifiable, so whatever happens after the > > change, could as well happen before it. > > > > I saw the references to the support code in e.g. ARM v7-A A2.7.5 > > Flush-to-zero. But I was sure that the text refers to the modes when > > e.g. FZ is cleared and UFE or IXE bits are enabled. In this situation, > > fault handler must do something to allow the computation to proceed. > > > > > > > > I don't think this is an issue for VFPv3 and later hardware. I've > > > looked in a few of the TRMs for different cortex-a series processors and > > > they say the hardware handles all combinations of rounding and flush to > > > zero without support software. But we should probably be on the lookout > > > for reports of misbehaving apps on RPi after this change, just in case > > > this setting has been protecting us from our ignorance there. > > > > I did found the reference to the support code in the VFP11 TRM, which in > > turns point to > > http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.epm049219/index.html > > Does FreeBSD enable and handle this variant of coprocessor ? If yes, then > > indeed I would need to not enable FZ on the affected hardware. > > > > That link opened a reference to a cortex-a57 chip for me. I've had > problems trying to share links to arm's documentation site, something > about the way that navbar stuff works makes pasting links not-work. I tried to reference App Notes and tutorials -> All Application Notes -> AN098 - VFP Support Code > > We support one arm11/VFPv2 chipset, the one used on RPi. It's the only > actual armv6 chip we support, all the other stuff supported by the arch > we call armv6 is really armv7. The TRM for the arm1176JZF-S core used > on RPi is the one that mentions needing support code. Yes, testing on original RPi, done by Glen, demostrates it. The test program I used is at https://www.kib.kiev.ua/kib/perl_opbasic_arith_175.c https://www.kib.kiev.ua/kib/perl_opbasic_arith_175 is the compiled binary with -mfloat-abi=softfp Also the following untested on RPi patch should fix this. I verified that it still starts with FZ bit cleared, on VFP v3 (RPi 2): https://www.kib.kiev.ua/kib/rpi-fz.1.patch
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