Date: Tue, 13 Sep 2016 18:52:19 +0300 From: Andriy Gapon <avg@FreeBSD.org> To: Konstantin Belousov <kostikbel@gmail.com> Cc: Slawa Olhovchenkov <slw@zxy.spb.ru>, stable@FreeBSD.org Subject: Re: X2APIC support Message-ID: <cb35f671-95e7-820f-6a78-ee60612cc1ad@FreeBSD.org> In-Reply-To: <20160913152240.GE38409@kib.kiev.ua> References: <20160912164412.GS34394@zxy.spb.ru> <5662c700-f139-4754-8693-7adc0f2657be@FreeBSD.org> <20160912175348.GV34394@zxy.spb.ru> <b03e7fa0-b73f-de92-b783-de8be2d66107@FreeBSD.org> <20160913121133.GX34394@zxy.spb.ru> <71a1f864-66de-0010-5024-e8e985f422f4@FreeBSD.org> <20160913124239.GZ34394@zxy.spb.ru> <c6e1a647-344b-a6d7-9f48-65092533ed21@FreeBSD.org> <20160913142118.GA34394@zxy.spb.ru> <37f5cebc-3fa1-9e95-5123-f3d8daa3130a@FreeBSD.org> <20160913152240.GE38409@kib.kiev.ua>
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On 13/09/2016 18:22, Konstantin Belousov wrote: > Any access > to the LAPIC registers page in x2APIC mode faults. Is this a fact? I read the following in the specification: In x2APIC mode, the memory mapped interface is not available and any access to the MMIO interface will behave similar to that of a legacy xAPIC in globally disabled state. But I couldn't find what actually happens for the legacy xAPIC in globally disabled state. For AMD processors it is documented that if xAPIC is disabled then accessing the APIC memory range works the same as accessing the regular memory. That can be different for Intel processors, of course. -- Andriy Gapon
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