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Date:      Wed, 04 Mar 1998 19:55:17 -0800
From:      Mike Smith <mike@smith.net.au>
To:        current@FreeBSD.ORG
Subject:   Re: silo overflows (Was Re: 3.0-RELEASE?) 
Message-ID:  <199803050355.TAA23983@dingo.cdrom.com>
In-Reply-To: Your message of "Wed, 04 Mar 1998 19:48:10 PST." <19980304194810.22210@hydrogen.nike.efn.org> 

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> Mike Smith scribbled this message on Mar 4:
> > > > 
> > > > I have a Pentium Pro 200 with 16650's (and the 16650's are detected) and
...
> > Interrupt rate is less significant in this issue than interrupt 
> > latency.  At 230kbps you have about 43us/character.  Without a 16650 
> > datasheet I can't confirm whether the standard FIFO trigger levels are 
> > doubled or not; if they are, you have 4 bytes or about 170us between 
> > when the interrupt is generated and "too late".
> 
> actually, the default for the 16550 is set to 14 characters.. and as
> there is a 16 character buffer, that means only 2 characters...

Note that the plaintiff was talking about 16650 parts, and an extended 
bitrate.  My naive assumption here is that the 16650 just doubles 
everything, leading to the same timing issue as with a 16550 at 115200.

> you might want to take a look at pr#2239...  it has a patch to change
> the default trigger level from 14 down to 8...  though the patch is
> slightly out of date (made to rev 1.154 of sio.c), it should be obvious
> what is needed...

The problem with this reduction (which has been implemented before) is 
that it increases the CPU load on systems with large numbers of ports.  
The FIFO trigger level tuning issue has seen a lot of water under the 
bridge - the driver used to adjust the level downwards in the presence 
of overflows, but this was abandoned for reasons best extracted from 
the CVS logs.

-- 
\\  Sometimes you're ahead,       \\  Mike Smith
\\  sometimes you're behind.      \\  mike@smith.net.au
\\  The race is long, and in the  \\  msmith@freebsd.org
\\  end it's only with yourself.  \\  msmith@cdrom.com



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