Date: Wed, 17 Jun 2009 16:34:40 +0000 (UTC) From: Nathan Whitehorn <nwhitehorn@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r194374 - in head/sys/powerpc: include powerpc Message-ID: <200906171634.n5HGYejl081352@svn.freebsd.org>
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Author: nwhitehorn Date: Wed Jun 17 16:34:40 2009 New Revision: 194374 URL: http://svn.freebsd.org/changeset/base/194374 Log: Teach cpu_est_clockrate() about the G5's slightly different PMC. This allows the boot messages to include the CPU speed and makes possible the forthcoming cpufreq support for the PPC 970. Modified: head/sys/powerpc/include/spr.h head/sys/powerpc/powerpc/cpu.c Modified: head/sys/powerpc/include/spr.h ============================================================================== --- head/sys/powerpc/include/spr.h Wed Jun 17 16:28:02 2009 (r194373) +++ head/sys/powerpc/include/spr.h Wed Jun 17 16:34:40 2009 (r194374) @@ -127,6 +127,8 @@ #define SPR_SPRG5 0x115 /* 4.. SPR General 5 */ #define SPR_SPRG6 0x116 /* 4.. SPR General 6 */ #define SPR_SPRG7 0x117 /* 4.. SPR General 7 */ +#define SPR_SCOMC 0x114 /* ... SCOM Address Register (970) */ +#define SPR_SCOMD 0x115 /* ... SCOM Data Register (970) */ #define SPR_ASR 0x118 /* ... Address Space Register (PPC64) */ #define SPR_EAR 0x11a /* .68 External Access Register */ #define SPR_PVR 0x11f /* 468 Processor Version Register */ @@ -302,6 +304,20 @@ #define SPR_DVC1 0x3b6 /* 4.. Data Value Compare 1 */ #define SPR_DVC2 0x3b7 /* 4.. Data Value Compare 2 */ #define SPR_MMCR0 0x3b8 /* .6. Monitor Mode Control Register 0 */ + +#define SPR_970MMCR0 0x31b /* ... Monitor Mode Control Register 0 (PPC 970) */ +#define SPR_970MMCR1 0x31e /* ... Monitor Mode Control Register 1 (PPC 970) */ +#define SPR_970MMCRA 0x312 /* ... Monitor Mode Control Register 2 (PPC 970) */ +#define SPR_970MMCR0 0x31b /* ... Monitor Mode Control Register 0 (PPC 970) */ +#define SPR_970PMC1 0x313 /* ... PMC 1 */ +#define SPR_970PMC2 0x314 /* ... PMC 2 */ +#define SPR_970PMC3 0x315 /* ... PMC 3 */ +#define SPR_970PMC4 0x316 /* ... PMC 4 */ +#define SPR_970PMC5 0x317 /* ... PMC 5 */ +#define SPR_970PMC6 0x318 /* ... PMC 6 */ +#define SPR_970PMC7 0x319 /* ... PMC 7 */ +#define SPR_970PMC8 0x31a /* ... PMC 8 */ + #define SPR_MMCR0_FC 0x80000000 /* Freeze counters */ #define SPR_MMCR0_FCS 0x40000000 /* Freeze counters in supervisor mode */ #define SPR_MMCR0_FCP 0x20000000 /* Freeze counters in user mode */ @@ -320,6 +336,8 @@ #define SPR_MMCR0_TRIGGER 0x00002000 /* Trigger */ #define SPR_MMCR0_PMC1SEL(x) ((x) << 6) /* PMC1 selector */ #define SPR_MMCR0_PMC2SEL(x) ((x) << 0) /* PMC2 selector */ +#define SPR_970MMCR0_PMC1SEL(x) ((x) << 6) /* PMC1 selector (970) */ +#define SPR_970MMCR0_PMC2SEL(x) ((x) << 1) /* PMC2 selector (970) */ #define SPR_SGR 0x3b9 /* 4.. Storage Guarded Register */ #define SPR_PMC1 0x3b9 /* .6. Performance Counter Register 1 */ #define SPR_DCWR 0x3ba /* 4.. Data Cache Write-through Register */ @@ -566,13 +584,18 @@ /* Performance counter declarations */ #define PMC_OVERFLOW 0x80000000 /* Counter has overflowed */ -/* The first five countable [non-]events are common to all the PMC's */ +/* The first five countable [non-]events are common to many PMC's */ #define PMCN_NONE 0 /* Count nothing */ #define PMCN_CYCLES 1 /* Processor cycles */ #define PMCN_ICOMP 2 /* Instructions completed */ #define PMCN_TBLTRANS 3 /* TBL bit transitions */ #define PCMN_IDISPATCH 4 /* Instructions dispatched */ +/* Similar things for the 970 PMC direct counters */ +#define PMC970N_NONE 0x8 /* Count nothing */ +#define PMC970N_CYCLES 0xf /* Processor cycles */ +#define PMC970N_ICOMP 0x9 /* Instructions completed */ + #if defined(AIM) #define SPR_ESR 0x3d4 /* 4.. Exception Syndrome Register */ Modified: head/sys/powerpc/powerpc/cpu.c ============================================================================== --- head/sys/powerpc/powerpc/cpu.c Wed Jun 17 16:28:02 2009 (r194373) +++ head/sys/powerpc/powerpc/cpu.c Wed Jun 17 16:34:40 2009 (r194374) @@ -277,6 +277,12 @@ cpu_setup(u_int cpuid) if (bootverbose) cpu_print_cacheinfo(cpuid, vers); break; + case IBM970: + case IBM970FX: + case IBM970MP: + cpu_print_speed(); + printf("\n"); + break; default: printf("\n"); break; @@ -299,8 +305,11 @@ int cpu_est_clockrate(int cpu_id, uint64_t *cps) { uint16_t vers; + register_t msr; vers = mfpvr() >> 16; + msr = mfmsr(); + mtmsr(msr & ~PSL_EE); switch (vers) { case MPC7450: @@ -315,11 +324,33 @@ cpu_est_clockrate(int cpu_id, uint64_t * mtspr(SPR_MMCR0, SPR_MMCR0_FC); mtspr(SPR_PMC1, 0); mtspr(SPR_MMCR0, SPR_MMCR0_PMC1SEL(PMCN_CYCLES)); - DELAY(100000); - *cps = (mfspr(SPR_PMC1) * 10) + 4999; + DELAY(1000); + *cps = (mfspr(SPR_PMC1) * 1000) + 4999; + mtspr(SPR_MMCR0, SPR_MMCR0_FC); + + mtmsr(msr); + return (0); + case IBM970: + case IBM970FX: + case IBM970MP: + isync(); + mtspr(SPR_970MMCR0, SPR_MMCR0_FC); + isync(); + mtspr(SPR_970MMCR1, 0); + mtspr(SPR_970MMCRA, 0); + mtspr(SPR_970PMC1, 0); + mtspr(SPR_970MMCR0, + SPR_970MMCR0_PMC1SEL(PMC970N_CYCLES)); + isync(); + DELAY(1000); + powerpc_sync(); + mtspr(SPR_970MMCR0, SPR_MMCR0_FC); + *cps = (mfspr(SPR_970PMC1) * 1000) + 4999; + + mtmsr(msr); return (0); } - + return (ENXIO); }
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