Date: Fri, 4 Jan 2008 16:21:22 GMT From: Rafal Jaworowski <raj@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 132492 for review Message-ID: <200801041621.m04GLMae015899@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=132492 Change 132492 by raj@raj_mimi on 2008/01/04 16:21:01 E500 pmap cleanup: Local routines -> static, eleminate unused code, style fixes. Affected files ... .. //depot/projects/e500/sys/powerpc/booke/pmap.c#5 edit .. //depot/projects/e500/sys/powerpc/include/tlb.h#2 edit Differences ... ==== //depot/projects/e500/sys/powerpc/booke/pmap.c#5 (text+ko) ==== @@ -191,15 +191,17 @@ /* Next free entry in the TLB1 */ static unsigned int tlb1_idx; +static tlbtid_t tid_alloc(struct pmap *); static void tid_flush(tlbtid_t); extern void tlb1_inval_va(vm_offset_t); extern void tlb0_inval_va(vm_offset_t); -extern void remap_ccsrbar(vm_offset_t, vm_offset_t, vm_offset_t); - static void tlb_print_entry(int, u_int32_t, u_int32_t, u_int32_t, u_int32_t); +static int tlb1_set_entry(vm_offset_t, vm_offset_t, vm_size_t, u_int32_t); +static void __tlb1_set_entry(unsigned int, vm_offset_t, vm_offset_t, + vm_size_t, u_int32_t, unsigned int, unsigned int); static void tlb1_write_entry(unsigned int); static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *); static vm_size_t tlb1_mapin_region(vm_offset_t, vm_offset_t, vm_size_t); @@ -208,6 +210,9 @@ static unsigned int size2tsize(vm_size_t); static unsigned int ilog2(unsigned int); +static void set_mas4_defaults(void); + +static void tlb0_inval_entry(vm_offset_t, unsigned int); static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int); static void tlb0_write_entry(unsigned int, unsigned int); static void tlb0_flush_entry(pmap_t, vm_offset_t); @@ -274,10 +279,10 @@ static __inline int pmap_track_modified(pmap_t pmap, vm_offset_t va) { - if (pmap == kernel_pmap) + if (pmap == kernel_pmap) return ((va < kmi.clean_sva) || (va >= kmi.clean_eva)); else - return (1); + return (1); } /* Return number of entries in TLB0. */ @@ -436,7 +441,7 @@ KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), ("ptbl_free: invalid pdir_idx")); - + ptbl = pmap->pm_pdir[pdir_idx]; //debugf("ptbl_free: ptbl = 0x%08x\n", (u_int32_t)ptbl); @@ -707,7 +712,7 @@ /* Get the page table pointer. */ ptbl = pmap->pm_pdir[pdir_idx]; - + if (ptbl) { /* * Check if there is valid mapping for requested @@ -1533,7 +1538,7 @@ hold_flag = PTBL_HOLD_FLAG(pmap); //debugf("pmap_remove: hold_flag = %d\n", hold_flag); - + vm_page_lock_queues(); PMAP_LOCK(pmap); for (; va < endva; va += PAGE_SIZE) { @@ -1979,7 +1984,7 @@ if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL) { if (!PTE_ISVALID(pte)) goto make_sure_to_unlock; - + if (!pmap_track_modified(pv->pv_pmap, pv->pv_va)) goto make_sure_to_unlock; @@ -2197,7 +2202,7 @@ vm_offset_t va; /* - * This currently does not work for entries that + * This currently does not work for entries that * overlap TLB1 entries. */ for (i = 0; i < tlb1_idx; i ++) { @@ -2314,7 +2319,7 @@ * Allocate a TID. If necessary, steal one from someone else. * The new TID is flushed from the TLB before returning. */ -tlbtid_t +static tlbtid_t tid_alloc(pmap_t pmap) { tlbtid_t tid; @@ -2336,7 +2341,7 @@ */ tid = next_tid; while (tidbusy[tid] != NULL) { - if (tid == next_tid) + if (tid == next_tid) break; if (tid == TID_MAX) @@ -2368,10 +2373,11 @@ return tid; } +#if 0 /* * Free this pmap's TID. */ -void +static void tid_free(pmap_t pmap) { tlbtid_t oldtid; @@ -2395,8 +2401,10 @@ tidbusy[oldtid] = NULL; tid_flush(oldtid); } +#endif -void +#ifdef DEBUG +static void tid_print_busy(void) { int i; @@ -2409,6 +2417,7 @@ } } +#endif /* DEBUG */ /**************************************************************************/ /* TLB0 handling */ @@ -2440,7 +2449,7 @@ tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; size = 0; - if (tsize) + if (tsize) size = tsize2size(tsize); debugf("%3d: (%s) [AS=%d] " @@ -2468,7 +2477,7 @@ tlb0_write_entry(unsigned int idx, unsigned int way) { u_int32_t mas0, mas7, nv; - + /* Clear high order RPN bits. */ mas7 = 0; @@ -2477,7 +2486,7 @@ nv = mas0 & (TLB0_NWAYS - 1); /* Select entry. */ - mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way) | nv; + mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way) | nv; //debugf("tlb0_write_entry: s (idx=%d way=%d mas0=0x%08x " // "mas1=0x%08x mas2=0x%08x mas3=0x%08x)\n", @@ -2501,7 +2510,7 @@ /* * Invalidate TLB0 entry, clear correspondig tlb0 table element. */ -void +static void tlb0_inval_entry(vm_offset_t va, unsigned int way) { int idx = tlb0_tableidx(va, way); @@ -2567,35 +2576,36 @@ mtx_unlock_spin(&tlb0_mutex); } +#ifdef DEBUG /* Print out tlb0 entries for given va. */ -void +static void tlb0_print_tlbentries_va(vm_offset_t va) { - u_int32_t mas0, mas1, mas2, mas3, mas7; - int way, idx; + u_int32_t mas0, mas1, mas2, mas3, mas7; + int way, idx; - debugf("TLB0 entries for va = 0x%08x:\n", va); - for (way = 0; way < TLB0_NWAYS; way ++) { - mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); - mtspr(SPR_MAS0, mas0); - __asm volatile("isync"); + debugf("TLB0 entries for va = 0x%08x:\n", va); + for (way = 0; way < TLB0_NWAYS; way ++) { + mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); + mtspr(SPR_MAS0, mas0); + __asm volatile("isync"); - mas2 = va & MAS2_EPN; - mtspr(SPR_MAS2, mas2); - __asm volatile("isync; tlbre"); + mas2 = va & MAS2_EPN; + mtspr(SPR_MAS2, mas2); + __asm volatile("isync; tlbre"); - mas1 = mfspr(SPR_MAS1); - mas2 = mfspr(SPR_MAS2); - mas3 = mfspr(SPR_MAS3); - mas7 = mfspr(SPR_MAS7); + mas1 = mfspr(SPR_MAS1); + mas2 = mfspr(SPR_MAS2); + mas3 = mfspr(SPR_MAS3); + mas7 = mfspr(SPR_MAS7); - idx = tlb0_tableidx(va, way); - tlb_print_entry(idx, mas1, mas2, mas3, mas7); - } + idx = tlb0_tableidx(va, way); + tlb_print_entry(idx, mas1, mas2, mas3, mas7); + } } /* Print out contents of the MAS registers for each TLB0 entry */ -void +static void tlb0_print_tlbentries(void) { u_int32_t mas0, mas1, mas2, mas3, mas7; @@ -2626,7 +2636,7 @@ } /* Print out kernel tlb0[] table. */ -void +static void tlb0_print_entries(void) { int i; @@ -2637,6 +2647,7 @@ tlb0[i].mas2, tlb0[i].mas3, 0); } } +#endif /* DEBUG */ /**************************************************************************/ /* TLB1 handling */ @@ -2649,7 +2660,7 @@ tlb1_write_entry(unsigned int idx) { u_int32_t mas0, mas7; - + //debugf("tlb1_write_entry: s\n"); /* Clear high order RPN bits */ @@ -2725,7 +2736,7 @@ * Entry TID is set to _tid which must not exceed 8 bit value. * Entry TS is set to either 0 or MAS1_TS based on provided _ts. */ -void +static void __tlb1_set_entry(unsigned int idx, vm_offset_t va, vm_offset_t pa, vm_size_t size, u_int32_t flags, unsigned int _tid, unsigned int _ts) { @@ -2763,7 +2774,7 @@ * Entries are created starting from index 0 (current free entry is * kept in tlb1_idx) and are not supposed to be invalidated. */ -int +static int tlb1_set_entry(vm_offset_t va, vm_offset_t pa, vm_size_t size, u_int32_t flags) { @@ -2791,7 +2802,7 @@ tlb1_inval_entry(unsigned int idx) { vm_offset_t va; - + va = tlb1[idx].mas2 & MAS2_EPN; tlb1[idx].mas1 = 0; /* !MAS1_VALID */ @@ -2920,7 +2931,7 @@ * Setup MAS4 defaults. * These values are loaded to MAS0-2 on a TLB miss. */ -void +static void set_mas4_defaults(void) { u_int32_t mas4; ==== //depot/projects/e500/sys/powerpc/include/tlb.h#2 (text+ko) ==== @@ -132,31 +132,11 @@ typedef u_int8_t tlbtid_t; struct pmap; -int tlb1_set_entry(vm_offset_t, vm_offset_t, - vm_size_t, u_int32_t); - -void __tlb1_set_entry(unsigned int, vm_offset_t, vm_offset_t, - vm_size_t, u_int32_t, unsigned int, unsigned int); - void tlb1_inval_entry(unsigned int); - void tlb1_init(vm_offset_t); - -void tlb0_print_tlbentries_va(vm_offset_t); void tlb1_print_entries(void); void tlb1_print_tlbentries(void); -void tlb0_inval_entry(vm_offset_t, unsigned int); - -void tlb0_print_entries(void); -void tlb0_print_tlbentries(void); - -void tid_print_busy(void); - -void set_mas4_defaults(void); - -tlbtid_t tid_alloc(struct pmap *); -void tid_free(struct pmap *); #endif /* !LOCORE */ #endif /* _MACHINE_TLB_H_ */
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