Date: Thu, 24 Jun 2010 14:17:10 +0000 (UTC) From: Nathan Whitehorn <nwhitehorn@FreeBSD.org> To: src-committers@freebsd.org, svn-src-projects@freebsd.org Subject: svn commit: r209507 - in projects/ppc64: share/mk sys/amd64/amd64 sys/amd64/ia32 sys/amd64/include sys/arm/conf sys/compat/x86bios sys/conf sys/dev/fb sys/i386/i386 sys/kern sys/mips/atheros sys/mi... Message-ID: <201006241417.o5OEHAiZ010847@svn.freebsd.org>
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Author: nwhitehorn Date: Thu Jun 24 14:17:10 2010 New Revision: 209507 URL: http://svn.freebsd.org/changeset/base/209507 Log: IFC @ 209506 Added: projects/ppc64/sys/conf/ldscript.mips.n32 - copied unchanged from r209506, head/sys/conf/ldscript.mips.n32 projects/ppc64/sys/mips/conf/XLRN32 - copied unchanged from r209506, head/sys/mips/conf/XLRN32 Modified: projects/ppc64/sys/amd64/amd64/exception.S projects/ppc64/sys/amd64/ia32/ia32_exception.S projects/ppc64/sys/amd64/include/asmacros.h projects/ppc64/sys/compat/x86bios/x86bios.c projects/ppc64/sys/compat/x86bios/x86bios.h projects/ppc64/sys/dev/fb/vesa.c projects/ppc64/sys/i386/i386/apic_vector.s projects/ppc64/sys/i386/i386/atpic_vector.s projects/ppc64/sys/i386/i386/exception.s projects/ppc64/sys/kern/subr_param.c projects/ppc64/sys/mips/atheros/ar71xxreg.h projects/ppc64/sys/mips/include/asm.h projects/ppc64/sys/mips/include/cpu.h projects/ppc64/sys/mips/include/pte.h projects/ppc64/sys/mips/include/setjmp.h projects/ppc64/sys/mips/include/vm.h projects/ppc64/sys/mips/include/vmparam.h projects/ppc64/sys/mips/mips/exception.S projects/ppc64/sys/mips/mips/machdep.c projects/ppc64/sys/mips/mips/pm_machdep.c projects/ppc64/sys/mips/mips/pmap.c projects/ppc64/sys/mips/mips/stack_machdep.c projects/ppc64/sys/mips/mips/trap.c projects/ppc64/sys/mips/mips/vm_machdep.c projects/ppc64/sys/netinet/sctp_pcb.c projects/ppc64/sys/powerpc/aim/nexus.c projects/ppc64/sys/powerpc/booke/pmap.c projects/ppc64/sys/powerpc/include/intr_machdep.h projects/ppc64/sys/powerpc/include/openpicvar.h projects/ppc64/sys/powerpc/mpc85xx/atpic.c projects/ppc64/sys/powerpc/mpc85xx/ocpbus.c projects/ppc64/sys/powerpc/mpc85xx/opic.c projects/ppc64/sys/powerpc/mpc85xx/pci_ocp.c projects/ppc64/sys/powerpc/powermac/cpcht.c projects/ppc64/sys/powerpc/powermac/openpic_macio.c projects/ppc64/sys/powerpc/powerpc/intr_machdep.c projects/ppc64/sys/powerpc/powerpc/openpic.c projects/ppc64/sys/powerpc/powerpc/pic_if.m projects/ppc64/usr.sbin/sysinstall/sysinstall.8 Directory Properties: projects/ppc64/ (props changed) projects/ppc64/cddl/contrib/opensolaris/ (props changed) projects/ppc64/contrib/ee/ (props changed) projects/ppc64/contrib/expat/ (props changed) projects/ppc64/contrib/file/ (props changed) projects/ppc64/contrib/gdb/ (props changed) projects/ppc64/contrib/gnu-sort/ (props changed) projects/ppc64/contrib/groff/ (props changed) projects/ppc64/contrib/less/ (props changed) projects/ppc64/contrib/libpcap/ (props changed) projects/ppc64/contrib/ncurses/ (props changed) projects/ppc64/contrib/one-true-awk/ (props changed) projects/ppc64/contrib/openbsm/ (props changed) projects/ppc64/contrib/openpam/ (props changed) projects/ppc64/contrib/pf/ (props changed) projects/ppc64/contrib/tcpdump/ (props changed) projects/ppc64/contrib/tcsh/ (props changed) projects/ppc64/contrib/tzcode/stdtime/ (props changed) projects/ppc64/contrib/tzcode/zic/ (props changed) projects/ppc64/contrib/tzdata/ (props changed) projects/ppc64/contrib/wpa/ (props changed) projects/ppc64/lib/libutil/ (props changed) projects/ppc64/lib/libz/ (props changed) projects/ppc64/sbin/ (props changed) projects/ppc64/sbin/ipfw/ (props changed) projects/ppc64/share/mk/bsd.arch.inc.mk (props changed) projects/ppc64/sys/ (props changed) projects/ppc64/sys/amd64/include/xen/ (props changed) projects/ppc64/sys/arm/conf/SHEEVAPLUG (props changed) projects/ppc64/sys/cddl/contrib/opensolaris/ (props changed) projects/ppc64/sys/contrib/dev/acpica/ (props changed) projects/ppc64/sys/contrib/x86emu/ (props changed) projects/ppc64/sys/dev/xen/xenpci/ (props changed) projects/ppc64/usr.bin/csup/ (props changed) projects/ppc64/usr.bin/procstat/ (props changed) Modified: projects/ppc64/sys/amd64/amd64/exception.S ============================================================================== --- projects/ppc64/sys/amd64/amd64/exception.S Thu Jun 24 13:17:45 2010 (r209506) +++ projects/ppc64/sys/amd64/amd64/exception.S Thu Jun 24 14:17:10 2010 (r209507) @@ -191,6 +191,7 @@ alltraps_pushregs_no_rdi: movq %r14,TF_R14(%rsp) movq %r15,TF_R15(%rsp) movl $TF_HASSEGS,TF_FLAGS(%rsp) + cld FAKE_MCOUNT(TF_RIP(%rsp)) #ifdef KDTRACE_HOOKS /* @@ -270,6 +271,7 @@ IDTVEC(dblfault) movw %es,TF_ES(%rsp) movw %ds,TF_DS(%rsp) movl $TF_HASSEGS,TF_FLAGS(%rsp) + cld testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */ jz 1f /* already running with kernel GS.base */ swapgs @@ -369,6 +371,7 @@ IDTVEC(fast_syscall) movq %r14,TF_R14(%rsp) /* C preserved */ movq %r15,TF_R15(%rsp) /* C preserved */ movl $TF_HASSEGS,TF_FLAGS(%rsp) + cld FAKE_MCOUNT(TF_RIP(%rsp)) movq %rsp,%rdi call syscall @@ -434,6 +437,7 @@ IDTVEC(nmi) movw %es,TF_ES(%rsp) movw %ds,TF_DS(%rsp) movl $TF_HASSEGS,TF_FLAGS(%rsp) + cld xorl %ebx,%ebx testb $SEL_RPL_MASK,TF_CS(%rsp) jnz nmi_fromuserspace Modified: projects/ppc64/sys/amd64/ia32/ia32_exception.S ============================================================================== --- projects/ppc64/sys/amd64/ia32/ia32_exception.S Thu Jun 24 13:17:45 2010 (r209506) +++ projects/ppc64/sys/amd64/ia32/ia32_exception.S Thu Jun 24 14:17:10 2010 (r209507) @@ -67,6 +67,7 @@ IDTVEC(int0x80_syscall) movq %r14,TF_R14(%rsp) movq %r15,TF_R15(%rsp) movl $TF_HASSEGS,TF_FLAGS(%rsp) + cld FAKE_MCOUNT(TF_RIP(%rsp)) movq %rsp, %rdi call ia32_syscall Modified: projects/ppc64/sys/amd64/include/asmacros.h ============================================================================== --- projects/ppc64/sys/amd64/include/asmacros.h Thu Jun 24 13:17:45 2010 (r209506) +++ projects/ppc64/sys/amd64/include/asmacros.h Thu Jun 24 14:17:10 2010 (r209507) @@ -166,7 +166,8 @@ movw %gs,TF_GS(%rsp) ; \ movw %es,TF_ES(%rsp) ; \ movw %ds,TF_DS(%rsp) ; \ - movl $TF_HASSEGS,TF_FLAGS(%rsp) + movl $TF_HASSEGS,TF_FLAGS(%rsp) ; \ + cld #define POP_FRAME \ movq TF_RDI(%rsp),%rdi ; \ Modified: projects/ppc64/sys/compat/x86bios/x86bios.c ============================================================================== --- projects/ppc64/sys/compat/x86bios/x86bios.c Thu Jun 24 13:17:45 2010 (r209506) +++ projects/ppc64/sys/compat/x86bios/x86bios.c Thu Jun 24 14:17:10 2010 (r209507) @@ -353,14 +353,14 @@ x86bios_emu_get_intr(struct x86emu *emu, } void * -x86bios_alloc(uint32_t *offset, size_t size) +x86bios_alloc(uint32_t *offset, size_t size, int flags) { void *vaddr; if (offset == NULL || size == 0) return (NULL); - vaddr = contigmalloc(size, M_DEVBUF, M_NOWAIT, X86BIOS_RAM_BASE, + vaddr = contigmalloc(size, M_DEVBUF, flags, X86BIOS_RAM_BASE, x86bios_rom_phys, X86BIOS_PAGE_SIZE, 0); if (vaddr != NULL) { *offset = vtophys(vaddr); Modified: projects/ppc64/sys/compat/x86bios/x86bios.h ============================================================================== --- projects/ppc64/sys/compat/x86bios/x86bios.h Thu Jun 24 13:17:45 2010 (r209506) +++ projects/ppc64/sys/compat/x86bios/x86bios.h Thu Jun 24 14:17:10 2010 (r209507) @@ -142,7 +142,7 @@ typedef struct x86regs x86regs_t; #define X86BIOS_PHYSTOOFF(x) ((x) & 0x000f) __BEGIN_DECLS -void *x86bios_alloc(uint32_t *offset, size_t size); +void *x86bios_alloc(uint32_t *offset, size_t size, int flags); void x86bios_call(struct x86regs *regs, uint16_t seg, uint16_t off); void x86bios_free(void *addr, size_t size); uint32_t x86bios_get_intr(int intno); Copied: projects/ppc64/sys/conf/ldscript.mips.n32 (from r209506, head/sys/conf/ldscript.mips.n32) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ projects/ppc64/sys/conf/ldscript.mips.n32 Thu Jun 24 14:17:10 2010 (r209507, copy of r209506, head/sys/conf/ldscript.mips.n32) @@ -0,0 +1,303 @@ +/*- + * Copyright (c) 2001, 2004, 2008, Juniper Networks, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Juniper Networks, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY JUNIPER NETWORKS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL JUNIPER NETWORKS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * JNPR: ldscript.mips,v 1.3 2006/10/11 06:12:04 + * $FreeBSD$ + */ + +OUTPUT_FORMAT("elf32-ntradbigmips", "elf32-ntradbigmips", + "elf32-ntradlittlemips") + +OUTPUT_ARCH(mips) +ENTRY(_start) +SEARCH_DIR(/usr/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; +PROVIDE (_DYNAMIC = 0); +*/ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = KERNLOADADDR + SIZEOF_HEADERS; + .text : + { + *(.trap) + *(.text) + *(.text.*) + *(.stub) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + *(.gnu.linkonce.t.*) + } =0x1000000 + .fini : + { + KEEP (*(.fini)) + } =0x1000000 + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + .rodata : { *(.rodata) *(.rodata.*) *(.gnu.linkonce.r.*) } + .rodata1 : { *(.rodata1) } + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .gnu.version : { *(.gnu.version) } + .gnu.version_d : { *(.gnu.version_d) } + .gnu.version_r : { *(.gnu.version_r) } + .rel.init : { *(.rel.init) } + .rela.init : { *(.rela.init) } + .rel.text : + { + *(.rel.text) + *(.rel.text.*) + *(.rel.gnu.linkonce.t.*) + } + .rela.text : + { + *(.rela.text) + *(.rela.text.*) + *(.rela.gnu.linkonce.t.*) + } + .rel.fini : { *(.rel.fini) } + .rela.fini : { *(.rela.fini) } + .rel.rodata : + { + *(.rel.rodata) + *(.rel.rodata.*) + *(.rel.gnu.linkonce.r.*) + } + .rela.rodata : + { + *(.rela.rodata) + *(.rela.rodata.*) + *(.rela.gnu.linkonce.r.*) + } + .rel.data : + { + *(.rel.data) + *(.rel.data.*) + *(.rel.gnu.linkonce.d.*) + } + .rela.data : + { + *(.rela.data) + *(.rela.data.*) + *(.rela.gnu.linkonce.d.*) + } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.sdata : + { + *(.rel.sdata) + *(.rel.sdata.*) + *(.rel.gnu.linkonce.s.*) + } + .rela.sdata : + { + *(.rela.sdata) + *(.rela.sdata.*) + *(.rela.gnu.linkonce.s.*) + } + .rel.sbss : + { + *(.rel.sbss) + *(.rel.sbss.*) + *(.rel.gnu.linkonce.sb.*) + } + .rela.sbss : + { + *(.rela.sbss) + *(.rela.sbss.*) + *(.rel.gnu.linkonce.sb.*) + } + .rel.sdata2 : + { + *(.rel.sdata2) + *(.rel.sdata2.*) + *(.rel.gnu.linkonce.s2.*) + } + .rela.sdata2 : + { + *(.rela.sdata2) + *(.rela.sdata2.*) + *(.rela.gnu.linkonce.s2.*) + } + .rel.sbss2 : + { + *(.rel.sbss2) + *(.rel.sbss2.*) + *(.rel.gnu.linkonce.sb2.*) + } + .rela.sbss2 : + { + *(.rela.sbss2) + *(.rela.sbss2.*) + *(.rela.gnu.linkonce.sb2.*) + } + .rel.bss : + { + *(.rel.bss) + *(.rel.bss.*) + *(.rel.gnu.linkonce.b.*) + } + .rela.bss : + { + *(.rela.bss) + *(.rela.bss.*) + *(.rela.gnu.linkonce.b.*) + } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : + { + KEEP (*(.init)) + } =0x1000000 + .reginfo : { *(.reginfo) } + .sdata2 : { *(.sdata2) *(.sdata2.*) *(.gnu.linkonce.s2.*) } + .sbss2 : { *(.sbss2) *(.sbss2.*) *(.gnu.linkonce.sb2.*) } + . = ALIGN(0x2000) + (. & (0x2000 - 1)); + .data : + { + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + SORT(CONSTRUCTORS) + } + .data1 : { *(.data1) } + .eh_frame : { KEEP (*(.eh_frame)) } + .gcc_except_table : { *(.gcc_except_table) } + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } + .plt : { *(.plt) } + _gp = ALIGN(16) + 0x7ff0; + .got : { *(.got.plt) *(.got) } + .dynamic : { *(.dynamic) } + /* We want the small data sections together, so single-instruction offsets + can access them all, and initialized data all before uninitialized, so + we can shorten the on-disk segment size. */ + .sdata : + { + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + } + _edata = .; + PROVIDE (edata = .); + __bss_start = .; + .sbss : + { + PROVIDE (__sbss_start = .); + PROVIDE (___sbss_start = .); + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + PROVIDE (__sbss_end = .); + PROVIDE (___sbss_end = .); + } + .bss : + { + *(.dynbss) + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ + . = ALIGN(64 / 8); + } + . = ALIGN(64 / 8); + _end = .; + PROVIDE (end = .); + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info) *(.gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + /* These must appear regardless of . */ +} Modified: projects/ppc64/sys/dev/fb/vesa.c ============================================================================== --- projects/ppc64/sys/dev/fb/vesa.c Thu Jun 24 13:17:45 2010 (r209506) +++ projects/ppc64/sys/dev/fb/vesa.c Thu Jun 24 14:17:10 2010 (r209507) @@ -164,7 +164,7 @@ static char *vesa_revstr = NULL; static int int10_set_mode(int mode); static int vesa_bios_post(void); -static int vesa_bios_get_mode(int mode, struct vesa_mode *vmode); +static int vesa_bios_get_mode(int mode, struct vesa_mode *vmode, int flags); static int vesa_bios_set_mode(int mode); #if 0 static int vesa_bios_get_dac(void); @@ -278,13 +278,13 @@ vesa_bios_post(void) /* VESA BIOS calls */ static int -vesa_bios_get_mode(int mode, struct vesa_mode *vmode) +vesa_bios_get_mode(int mode, struct vesa_mode *vmode, int flags) { x86regs_t regs; uint32_t offs; void *buf; - buf = x86bios_alloc(&offs, sizeof(*vmode)); + buf = x86bios_alloc(&offs, sizeof(*vmode), flags); if (buf == NULL) return (1); @@ -367,7 +367,7 @@ vesa_bios_save_palette(int start, int co u_char *p; int i; - p = (u_char *)x86bios_alloc(&offs, colors * 4); + p = (u_char *)x86bios_alloc(&offs, colors * 4, M_NOWAIT); if (p == NULL) return (1); @@ -407,7 +407,7 @@ vesa_bios_save_palette2(int start, int c u_char *p; int i; - p = (u_char *)x86bios_alloc(&offs, colors * 4); + p = (u_char *)x86bios_alloc(&offs, colors * 4, M_NOWAIT); if (p == NULL) return (1); @@ -446,7 +446,7 @@ vesa_bios_load_palette(int start, int co u_char *p; int i; - p = (u_char *)x86bios_alloc(&offs, colors * 4); + p = (u_char *)x86bios_alloc(&offs, colors * 4, M_NOWAIT); if (p == NULL) return (1); @@ -481,7 +481,7 @@ vesa_bios_load_palette2(int start, int c u_char *p; int i; - p = (u_char *)x86bios_alloc(&offs, colors * 4); + p = (u_char *)x86bios_alloc(&offs, colors * 4, M_NOWAIT); if (p == NULL) return (1); @@ -535,7 +535,7 @@ vesa_bios_save_restore(int code, void *p if (code != STATE_SAVE && code != STATE_LOAD) return (1); - buf = x86bios_alloc(&offs, size); + buf = x86bios_alloc(&offs, size, M_NOWAIT); x86bios_init_regs(®s); regs.R_AX = 0x4f04; @@ -800,9 +800,7 @@ vesa_bios_init(void) x86bios_init_regs(®s); regs.R_AX = 0x4f00; - vmbuf = x86bios_alloc(&offs, sizeof(*buf)); - if (vmbuf == NULL) - return (1); + vmbuf = x86bios_alloc(&offs, sizeof(*buf), M_WAITOK); regs.R_ES = X86BIOS_PHYSTOSEG(offs); regs.R_DI = X86BIOS_PHYSTOOFF(offs); @@ -858,7 +856,7 @@ vesa_bios_init(void) for (i = 0, modes = 0; (i < (M_VESA_MODE_MAX - M_VESA_BASE + 1)) && (vesa_vmodetab[i] != 0xffff); ++i) { vesa_vmodetab[i] = le16toh(vesa_vmodetab[i]); - if (vesa_bios_get_mode(vesa_vmodetab[i], &vmode)) + if (vesa_bios_get_mode(vesa_vmodetab[i], &vmode, M_WAITOK)) continue; vmode.v_modeattr = le16toh(vmode.v_modeattr); @@ -1790,7 +1788,7 @@ vesa_bios_info(int level) for (i = 0; (i < (M_VESA_MODE_MAX - M_VESA_BASE + 1)) && (vesa_vmodetab[i] != 0xffff); ++i) { - if (vesa_bios_get_mode(vesa_vmodetab[i], &vmode)) + if (vesa_bios_get_mode(vesa_vmodetab[i], &vmode, M_NOWAIT)) continue; /* print something for diagnostic purpose */ Modified: projects/ppc64/sys/i386/i386/apic_vector.s ============================================================================== --- projects/ppc64/sys/i386/i386/apic_vector.s Thu Jun 24 13:17:45 2010 (r209506) +++ projects/ppc64/sys/i386/i386/apic_vector.s Thu Jun 24 14:17:10 2010 (r209507) @@ -56,6 +56,7 @@ IDTVEC(vec_name) ; \ PUSH_FRAME ; \ SET_KERNEL_SREGS ; \ + cld ; \ FAKE_MCOUNT(TF_EIP(%esp)) ; \ movl lapic, %edx ; /* pointer to local APIC */ \ movl LA_ISR + 16 * (index)(%edx), %eax ; /* load ISR */ \ @@ -103,6 +104,7 @@ IDTVEC(spuriousint) IDTVEC(timerint) PUSH_FRAME SET_KERNEL_SREGS + cld FAKE_MCOUNT(TF_EIP(%esp)) pushl %esp call lapic_handle_timer @@ -118,6 +120,7 @@ IDTVEC(timerint) IDTVEC(cmcint) PUSH_FRAME SET_KERNEL_SREGS + cld FAKE_MCOUNT(TF_EIP(%esp)) call lapic_handle_cmc MEXITCOUNT @@ -131,6 +134,7 @@ IDTVEC(cmcint) IDTVEC(errorint) PUSH_FRAME SET_KERNEL_SREGS + cld FAKE_MCOUNT(TF_EIP(%esp)) call lapic_handle_error MEXITCOUNT @@ -302,6 +306,7 @@ IDTVEC(invlcache) IDTVEC(ipi_intr_bitmap_handler) PUSH_FRAME SET_KERNEL_SREGS + cld movl lapic, %edx movl $0, LA_EOI(%edx) /* End Of Interrupt to APIC */ @@ -320,6 +325,7 @@ IDTVEC(ipi_intr_bitmap_handler) IDTVEC(cpustop) PUSH_FRAME SET_KERNEL_SREGS + cld movl lapic, %eax movl $0, LA_EOI(%eax) /* End Of Interrupt to APIC */ @@ -339,6 +345,7 @@ IDTVEC(cpustop) IDTVEC(rendezvous) PUSH_FRAME SET_KERNEL_SREGS + cld #ifdef COUNT_IPIS movl PCPU(CPUID), %eax @@ -360,6 +367,7 @@ IDTVEC(rendezvous) IDTVEC(lazypmap) PUSH_FRAME SET_KERNEL_SREGS + cld call pmap_lazyfix_action Modified: projects/ppc64/sys/i386/i386/atpic_vector.s ============================================================================== --- projects/ppc64/sys/i386/i386/atpic_vector.s Thu Jun 24 13:17:45 2010 (r209506) +++ projects/ppc64/sys/i386/i386/atpic_vector.s Thu Jun 24 14:17:10 2010 (r209507) @@ -49,6 +49,7 @@ IDTVEC(vec_name) ; \ PUSH_FRAME ; \ SET_KERNEL_SREGS ; \ + cld ; \ ; \ FAKE_MCOUNT(TF_EIP(%esp)) ; \ pushl %esp ; \ Modified: projects/ppc64/sys/i386/i386/exception.s ============================================================================== --- projects/ppc64/sys/i386/i386/exception.s Thu Jun 24 13:17:45 2010 (r209506) +++ projects/ppc64/sys/i386/i386/exception.s Thu Jun 24 14:17:10 2010 (r209507) @@ -159,6 +159,7 @@ alltraps: pushl %fs alltraps_with_regs_pushed: SET_KERNEL_SREGS + cld FAKE_MCOUNT(TF_EIP(%esp)) calltrap: pushl %esp @@ -233,6 +234,7 @@ IDTVEC(lcall_syscall) pushl %es pushl %fs SET_KERNEL_SREGS + cld FAKE_MCOUNT(TF_EIP(%esp)) pushl %esp call syscall @@ -256,6 +258,7 @@ IDTVEC(int0x80_syscall) pushl %es pushl %fs SET_KERNEL_SREGS + cld FAKE_MCOUNT(TF_EIP(%esp)) pushl %esp call syscall Modified: projects/ppc64/sys/kern/subr_param.c ============================================================================== --- projects/ppc64/sys/kern/subr_param.c Thu Jun 24 13:17:45 2010 (r209506) +++ projects/ppc64/sys/kern/subr_param.c Thu Jun 24 14:17:10 2010 (r209507) @@ -53,10 +53,10 @@ __FBSDID("$FreeBSD$"); */ #ifndef HZ -# if defined(__amd64__) || defined(__i386__) || defined(__ia64__) || defined(__sparc64__) -# define HZ 1000 -# else +# if defined(__mips__) || defined(__arm__) # define HZ 100 +# else +# define HZ 1000 # endif # ifndef HZ_VM # define HZ_VM 100 Modified: projects/ppc64/sys/mips/atheros/ar71xxreg.h ============================================================================== --- projects/ppc64/sys/mips/atheros/ar71xxreg.h Thu Jun 24 13:17:45 2010 (r209506) +++ projects/ppc64/sys/mips/atheros/ar71xxreg.h Thu Jun 24 14:17:10 2010 (r209507) @@ -152,7 +152,9 @@ #define GPIO_FUNC_STEREO_EN (1 << 17) #define GPIO_FUNC_SLIC_EN (1 << 16) #define GPIO_FUNC_SPI_CS1_EN (1 << 15) + /* CS1 is shared with GPIO_1 */ #define GPIO_FUNC_SPI_CS0_EN (1 << 14) + /* CS0 is shared with GPIO_0 */ #define GPIO_FUNC_SPI_EN (1 << 13) #define GPIO_FUNC_UART_EN (1 << 8) #define GPIO_FUNC_USB_OC_EN (1 << 4) Copied: projects/ppc64/sys/mips/conf/XLRN32 (from r209506, head/sys/mips/conf/XLRN32) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ projects/ppc64/sys/mips/conf/XLRN32 Thu Jun 24 14:17:10 2010 (r209507, copy of r209506, head/sys/mips/conf/XLRN32) @@ -0,0 +1,133 @@ +# XLRN32 -- Kernel configuration file for N32 kernel on XLR/XLS +# +# For more information on this file, please read the handbook section on +# Kernel Configuration Files: +# +# http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html +# +# The handbook is also available locally in /usr/share/doc/handbook +# if you've installed the doc distribution, otherwise always see the +# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the +# latest information. +# +# An exhaustive list of options and more detailed explanations of the +# device lines is also present in the ../../conf/NOTES and NOTES files. +# If you are in doubt as to the purpose or necessity of a line, check first +# in NOTES. +# +# $FreeBSD$ + +machine mips +cpu CPU_MIPS4KC +ident XLR + +makeoptions MODULES_OVERRIDE="" +makeoptions TARGET_BIG_ENDIAN + +include "../rmi/std.xlr" + +makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols +makeoptions ARCH_FLAGS="-march=mips64 -mabi=n32" +makeoptions LDSCRIPT_NAME=ldscript.mips.n32 + +#profile 2 + +options SCHED_ULE # ULE scheduler +#options VERBOSE_SYSINIT +#options SCHED_4BSD # 4BSD scheduler +options SMP +options PREEMPTION # Enable kernel thread preemption +#options FULL_PREEMPTION # Enable kernel thread preemption +options INET # InterNETworking +options INET6 # IPv6 communications protocols +options FFS # Berkeley Fast Filesystem +#options SOFTUPDATES # Enable FFS soft updates support +options UFS_ACL # Support for access control lists +options UFS_DIRHASH # Improve performance on big directories +options NFSCLIENT +options NFS_ROOT +# +options BOOTP +options BOOTP_NFSROOT +options BOOTP_NFSV3 +options BOOTP_WIRED_TO=rge0 +options BOOTP_COMPAT +options ROOTDEVNAME=\"nfs:10.1.1.8:/usr/extra/nfsroot\" +# +#options MD_ROOT # MD is a potential root device +#options MD_ROOT_SIZE=27000 +#options MD_ROOT_SIZE=5120 +#options ROOTDEVNAME=\"ufs:md0\" +options _KPOSIX_PRIORITY_SCHEDULING # POSIX P1003_1B real-time extensions +options HZ=1000 +options NO_SWAPPING + +#Debugging options +options KTRACE # ktrace(1) support +options DDB +options KDB +options GDB +options ALT_BREAK_TO_DEBUGGER +#options DEADLKRES #Enable the deadlock resolver +options INVARIANTS #Enable calls of extra sanity checking +options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS +#options WITNESS #Enable checks to detect deadlocks and cycles +#options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed +#options KTR # ktr(4) and ktrdump(8) support +#options KTR_COMPILE=(KTR_LOCK|KTR_PROC|KTR_INTR|KTR_CALLOUT|KTR_UMA|KTR_SYSC|KTR_CRITICAL) +#options KTR_ENTRIES=131072 +#options MUTEX_DEBUG +#options MUTEX_PROFILING + +device pci +#device ata +#device atadisk +#options XLR_PERFMON # Enable XLR processor activity monitoring +options BREAK_TO_DEBUGGER +#device genclock +device uart +# Pseudo +device loop +device random +device md +device mem +device pty +device bpf + +# Network +device miibus +device rge +device ether +device re +device msk + +device da +device scbus +#device ohci # OHCI PCI->USB interface +device ehci # EHCI PCI->USB interface (USB 2.0) +device usb # USB Bus (required) +options USB_DEBUG # enable debug msgs +#device udbp # USB Double Bulk Pipe devices +#device ugen # Generic +#device uhid # "Human Interface Devices" +device umass # Disks/Mass storage - Requires scbus and da + +#device cfi + +#i2c +# Not yet +#device ic +#device iic +#device iicbb +#device iicbus +#device xlr_rtc +#device xlr_temperature +#device xlr_eeprom + +#crypto +# Not yet +#device cryptodev +#device crypto +#device rmisec +options ISA_MIPS64 +makeoptions KERNLOADADDR=0x80100000 Modified: projects/ppc64/sys/mips/include/asm.h ============================================================================== --- projects/ppc64/sys/mips/include/asm.h Thu Jun 24 13:17:45 2010 (r209506) +++ projects/ppc64/sys/mips/include/asm.h Thu Jun 24 14:17:10 2010 (r209507) @@ -806,10 +806,11 @@ _C_LABEL(x): * 9 S7 * 10 SP * 11 S8 - * 12 signal mask (dependant on magic) - * 13 (con't) + * 12 GP (dependent on ABI) + * 13 signal mask (dependant on magic) * 14 (con't) * 15 (con't) + * 16 (con't) * * The magic number number identifies the jmp_buf and * how the buffer was created as well as providing @@ -834,9 +835,12 @@ _C_LABEL(x): #define _JB_REG_S7 9 #define _JB_REG_SP 10 #define _JB_REG_S8 11 +#if defined(__mips_n32) || defined(__mips_n64) +#define _JB_REG_GP 12 +#endif /* Only valid with the _JB_MAGIC_SETJMP magic */ -#define _JB_SIGMASK 12 +#define _JB_SIGMASK 13 #endif /* !_MACHINE_ASM_H_ */ Modified: projects/ppc64/sys/mips/include/cpu.h ============================================================================== --- projects/ppc64/sys/mips/include/cpu.h Thu Jun 24 13:17:45 2010 (r209506) +++ projects/ppc64/sys/mips/include/cpu.h Thu Jun 24 14:17:10 2010 (r209507) @@ -49,7 +49,7 @@ #include <machine/endian.h> -#define MIPS_KSEG0_LARGEST_PHYS 0x20000000 +#define MIPS_KSEG0_LARGEST_PHYS (0x20000000) #define MIPS_PHYS_MASK (0x1fffffff) #define MIPS_PHYS_TO_KSEG0(x) ((uintptr_t)(x) | MIPS_KSEG0_START) @@ -162,11 +162,11 @@ /* * Location of exception vectors. */ -#define RESET_EXC_VEC 0xbfc00000 -#define TLB_MISS_EXC_VEC 0x80000000 -#define XTLB_MISS_EXC_VEC 0x80000080 -#define CACHE_ERR_EXC_VEC 0x80000100 -#define GEN_EXC_VEC 0x80000180 +#define RESET_EXC_VEC ((intptr_t)(int32_t)0xbfc00000) +#define TLB_MISS_EXC_VEC ((intptr_t)(int32_t)0x80000000) +#define XTLB_MISS_EXC_VEC ((intptr_t)(int32_t)0x80000080) +#define CACHE_ERR_EXC_VEC ((intptr_t)(int32_t)0x80000100) +#define GEN_EXC_VEC ((intptr_t)(int32_t)0x80000180) /* * Coprocessor 0 registers: Modified: projects/ppc64/sys/mips/include/pte.h ============================================================================== --- projects/ppc64/sys/mips/include/pte.h Thu Jun 24 13:17:45 2010 (r209506) +++ projects/ppc64/sys/mips/include/pte.h Thu Jun 24 14:17:10 2010 (r209507) @@ -32,7 +32,7 @@ /* * TLB and PTE management. Most things operate within the context of * EntryLo0,1, and begin with TLBLO_. Things which work with EntryHi - * start with TLBHI_. PTE bits begin with PG_. + * start with TLBHI_. PTE bits begin with PTE_. * * Note that we use the same size VM and TLB pages. */ @@ -63,7 +63,7 @@ #define TLBLO_PFN_TO_PA(pfn) ((vm_paddr_t)((pfn) >> TLBLO_PFN_SHIFT) << TLB_PAGE_SHIFT) #define TLBLO_PTE_TO_PFN(pte) ((pte) & TLBLO_PFN_MASK) #define TLBLO_PTE_TO_PA(pte) (TLBLO_PFN_TO_PA(TLBLO_PTE_TO_PFN((pte)))) - + /* * VPN for EntryHi register. Upper two bits select user, supervisor, * or kernel. Bits 61 to 40 copy bit 63. VPN2 is bits 39 and down to @@ -76,54 +76,57 @@ #define TLBHI_ENTRY(va, asid) (((va) & ~PAGE_MASK) | ((asid) & TLBHI_ASID_MASK)) #ifndef _LOCORE -typedef unsigned int pt_entry_t; -typedef pt_entry_t *pd_entry_t; +typedef uint32_t pt_entry_t; +typedef pt_entry_t *pd_entry_t; #endif #define PDESIZE sizeof(pd_entry_t) /* for assembly files */ #define PTESIZE sizeof(pt_entry_t) /* for assembly files */ -#define PT_ENTRY_NULL ((pt_entry_t *) 0) - -#define PTE_WIRED 0x80000000 /* SW */ -#define PTE_W PTE_WIRED -#define PTE_RO 0x40000000 /* SW */ - -#define PTE_G 0x00000001 /* HW */ -#define PTE_V 0x00000002 -/*#define PTE_NV 0x00000000 Not Used */ -#define PTE_M 0x00000004 -#define PTE_RW PTE_M -#define PTE_ODDPG 0x00001000 -/*#define PG_ATTR 0x0000003f Not Used */ -#define PTE_UNCACHED 0x00000010 -#ifdef CPU_SB1 -#define PTE_CACHE 0x00000028 /* cacheable coherent */ +/* + * TLB flags managed in hardware: + * C: Cache attribute. + * D: Dirty bit. This means a page is writable. It is not + * set at first, and a write is trapped, and the dirty + * bit is set. See also PTE_RO. + * V: Valid bit. Obvious, isn't it? + * G: Global bit. This means that this mapping is present + * in EVERY address space, and to ignore the ASID when + * it is matched. + */ +#define PTE_C(attr) ((attr & 0x07) << 3) +#define PTE_C_UNCACHED (PTE_C(0x02)) +/* + * The preferred cache attribute for cacheable pages, this can be + * implementation dependent. We will use the standard value 0x3 as + * default. + */ +#if defined(CPU_SB1) +#define PTE_C_CACHE (PTE_C(0x05)) #else -#define PTE_CACHE 0x00000018 +#define PTE_C_CACHE (PTE_C(0x03)) #endif -/*#define PG_CACHEMODE 0x00000038 Not Used*/ -#define PTE_ROPAGE (PTE_V | PTE_RO | PTE_CACHE) /* Write protected */ -#define PTE_RWPAGE (PTE_V | PTE_M | PTE_CACHE) /* Not wr-prot not clean */ -#define PTE_CWPAGE (PTE_V | PTE_CACHE) /* Not wr-prot but clean */ -#define PTE_IOPAGE (PTE_G | PTE_V | PTE_M | PTE_UNCACHED) -#define PTE_FRAME 0x3fffffc0 -#define PTE_HVPN 0xffffe000 /* Hardware page no mask */ -#define PTE_ASID 0x000000ff /* Address space ID */ - - -/* User virtual to pte offset in page table */ -#define vad_to_pte_offset(adr) (((adr) >> PAGE_SHIFT) & (NPTEPG -1)) - -#define mips_pg_v(entry) ((entry) & PTE_V) -#define mips_pg_wired(entry) ((entry) & PTE_WIRED) -#define mips_pg_m_bit() (PTE_M) -#define mips_pg_rw_bit() (PTE_M) -#define mips_pg_ro_bit() (PTE_RO) -#define mips_pg_ropage_bit() (PTE_ROPAGE) -#define mips_pg_rwpage_bit() (PTE_RWPAGE) -#define mips_pg_cwpage_bit() (PTE_CWPAGE) -#define mips_pg_global_bit() (PTE_G) -#define mips_pg_wired_bit() (PTE_WIRED) +#define PTE_D 0x04 +#define PTE_V 0x02 +#define PTE_G 0x01 + +/* + * VM flags managed in software: + * RO: Read only. Never set PTE_D on this page, and don't + * listen to requests to write to it. + * W: Wired. ??? + */ +#define PTE_RO (0x01 << TLBLO_SWBITS_SHIFT) +#define PTE_W (0x02 << TLBLO_SWBITS_SHIFT) + +/* + * PTE management functions for bits defined above. + * + * XXX Can make these atomics, but some users of them are using PTEs in local + * registers and such and don't need the overhead. + */ +#define pte_clear(pte, bit) (*(pte) &= ~(bit)) +#define pte_set(pte, bit) (*(pte) |= (bit)) +#define pte_test(pte, bit) ((*(pte) & (bit)) == (bit)) #endif /* !_MACHINE_PTE_H_ */ Modified: projects/ppc64/sys/mips/include/setjmp.h ============================================================================== --- projects/ppc64/sys/mips/include/setjmp.h Thu Jun 24 13:17:45 2010 (r209506) +++ projects/ppc64/sys/mips/include/setjmp.h Thu Jun 24 14:17:10 2010 (r209507) @@ -39,7 +39,7 @@ #include <sys/cdefs.h> -#define _JBLEN 95 /* size, in longs, of a jmp_buf */ +#define _JBLEN 95 /* size, in longs (or long longs), of a jmp_buf */ /* * jmp_buf and sigjmp_buf are encapsulated in different structs to force @@ -49,10 +49,18 @@ #ifndef _LOCORE #ifndef __ASSEMBLER__ #if __BSD_VISIBLE || __POSIX_VISIBLE || __XSI_VISIBLE +#ifdef __mips_n32 +typedef struct _sigjmp_buf { long long _sjb[_JBLEN + 1]; } sigjmp_buf[1]; +#else typedef struct _sigjmp_buf { long _sjb[_JBLEN + 1]; } sigjmp_buf[1]; #endif +#endif +#ifdef __mips_n32 +typedef struct _jmp_buf { long long _jb[_JBLEN + 1]; } jmp_buf[1]; +#else typedef struct _jmp_buf { long _jb[_JBLEN + 1]; } jmp_buf[1]; +#endif #endif /* __ASSEMBLER__ */ #endif /* _LOCORE */ Modified: projects/ppc64/sys/mips/include/vm.h ============================================================================== --- projects/ppc64/sys/mips/include/vm.h Thu Jun 24 13:17:45 2010 (r209506) +++ projects/ppc64/sys/mips/include/vm.h Thu Jun 24 14:17:10 2010 (r209507) @@ -32,9 +32,7 @@ #include <machine/pte.h> /* Memory attributes. */ -#define VM_MEMATTR_UNCACHED ((vm_memattr_t)PTE_UNCACHED) -#define VM_MEMATTR_CACHEABLE_NONCOHERENT ((vm_memattr_t)PTE_CACHE) - -#define VM_MEMATTR_DEFAULT VM_MEMATTR_CACHEABLE_NONCOHERENT +#define VM_MEMATTR_UNCACHED ((vm_memattr_t)PTE_C_UNCACHED) +#define VM_MEMATTR_DEFAULT ((vm_memattr_t)PTE_C_CACHE) #endif /* !_MACHINE_VM_H_ */ Modified: projects/ppc64/sys/mips/include/vmparam.h ============================================================================== --- projects/ppc64/sys/mips/include/vmparam.h Thu Jun 24 13:17:45 2010 (r209506) +++ projects/ppc64/sys/mips/include/vmparam.h Thu Jun 24 14:17:10 2010 (r209507) @@ -100,11 +100,17 @@ #define VM_MAX_ADDRESS ((vm_offset_t)(intptr_t)(int32_t)0xffffffff) #define VM_MINUSER_ADDRESS ((vm_offset_t)0x00000000) -#define VM_MAXUSER_ADDRESS ((vm_offset_t)0x80000000) #define VM_MAX_MMAP_ADDR VM_MAXUSER_ADDRESS -#define VM_MIN_KERNEL_ADDRESS ((vm_offset_t)0xC0000000) -#define VM_MAX_KERNEL_ADDRESS ((vm_offset_t)0xFFFFC000) +#if defined(__mips_n64) +#define VM_MAXUSER_ADDRESS (VM_MINUSER_ADDRESS + (NPDEPG * NPTEPG * PAGE_SIZE)) +#define VM_MIN_KERNEL_ADDRESS ((vm_offset_t)0xc000000000000000) +#define VM_MAX_KERNEL_ADDRESS (VM_MIN_KERNEL_ADDRESS + (NPDEPG * NPTEPG * PAGE_SIZE)) +#else +#define VM_MAXUSER_ADDRESS ((vm_offset_t)0x80000000) +#define VM_MIN_KERNEL_ADDRESS ((vm_offset_t)0xC0000000) +#define VM_MAX_KERNEL_ADDRESS ((vm_offset_t)0xFFFFC000) *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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