Date: Tue, 31 Oct 2017 23:17:17 +0000 (UTC) From: Andrew Turner <andrew@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r325251 - head/sys/arm64/arm64 Message-ID: <201710312317.v9VNHH7W069090@repo.freebsd.org>
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Author: andrew Date: Tue Oct 31 23:17:17 2017 New Revision: 325251 URL: https://svnweb.freebsd.org/changeset/base/325251 Log: Allocate the ITS translation table with a 64k page alignment. This is the largest alignment the ITS can require. This fixes a bug with the ARM Architecture Envelope Model (AEM) where it only allows 64k pages so will fail to attach the ITS device when this table is not sufficiently aligned. Sponsored by: DARPA, AFRL Modified: head/sys/arm64/arm64/gicv3_its.c Modified: head/sys/arm64/arm64/gicv3_its.c ============================================================================== --- head/sys/arm64/arm64/gicv3_its.c Tue Oct 31 22:12:14 2017 (r325250) +++ head/sys/arm64/arm64/gicv3_its.c Tue Oct 31 23:17:17 2017 (r325251) @@ -457,7 +457,7 @@ gicv3_its_table_init(device_t dev, struct gicv3_its_so /* Allocate the table */ table = (vm_offset_t)contigmalloc(npages * PAGE_SIZE, M_GICV3_ITS, M_WAITOK | M_ZERO, 0, (1ul << 48) - 1, - PAGE_SIZE, 0); + PAGE_SIZE_64K, 0); sc->sc_its_ptab[i].ptab_vaddr = table; sc->sc_its_ptab[i].ptab_size = npages * PAGE_SIZE;
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