Date: Tue, 13 Jun 2006 18:05:17 +0200 From: Per =?iso-8859-1?q?Fogelstr=F6m?= <pefo@opsycon.se> To: rmk@rmkhome.com Cc: John Nemeth <jnemeth@victoria.tc.ca>, misc@openbsd.org, Otto Moerbeek <otto@drijf.net>, Ted Unangst <ted.unangst@gmail.com>, Ted Mittelstaedt <tedm@toybox.placo.com>, Marcus Watts <mdw@umich.edu>, freebsd-questions@freebsd.org, =?iso-8859-1?q?H=E1morszky?= =?iso-8859-1?q?_Bal=E1zs?= <balihb@ogyi.hu>, Johnny Billquist <bqt@update.uu.se>, netbsd-users@netbsd.org, Nikolas Britton <nikolas.britton@gmail.com> Subject: Re: wikipedia article Message-ID: <200606131805.18778.pefo@opsycon.se> In-Reply-To: <200606131223.k5DCNkcB021980@toad.rmkhome.com> References: <200606131223.k5DCNkcB021980@toad.rmkhome.com>
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On Tuesday 13 June 2006 14:23, Rick Kelly wrote: > Johnny Billquist said: > >> There's actually a cheesy way to do demand paging with microprocessors > >> that don't support demand paging (such as the original 68000--another > >> "16 bit" machine). The way to do this is to run two processors in > >> parallel but skewed by one instruction. If the first one does a bad > >> memory fetch, then the second one will not have fetched the instruction > >> causing the fault so contains restartable machine state. Masscomp sold > >> a machine like this once. > > > >Didn't the first Apollos do this? > > And also the Sun 1. IIRC it was simpler than that. When the first cpu caused a 'miss' it was put in wait and cpu 2 handled the pagein and then released cpu 1. Keeping the two cpus synched, one instruction apart would have been too complicated if not impossible...
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