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Date:      Tue, 20 Oct 2015 01:46:06 +0000 (UTC)
From:      "Conrad E. Meyer" <cem@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org
Subject:   svn commit: r289610 - head/sys/dev/ntb/ntb_hw
Message-ID:  <201510200146.t9K1k6AV027438@repo.freebsd.org>

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Author: cem
Date: Tue Oct 20 01:46:05 2015
New Revision: 289610
URL: https://svnweb.freebsd.org/changeset/base/289610

Log:
  NTB: enum-ify some HW constants
  
  Sponsored by:	EMC / Isilon Storage Division

Modified:
  head/sys/dev/ntb/ntb_hw/ntb_hw.c
  head/sys/dev/ntb/ntb_hw/ntb_regs.h

Modified: head/sys/dev/ntb/ntb_hw/ntb_hw.c
==============================================================================
--- head/sys/dev/ntb/ntb_hw/ntb_hw.c	Tue Oct 20 01:45:57 2015	(r289609)
+++ head/sys/dev/ntb/ntb_hw/ntb_hw.c	Tue Oct 20 01:46:05 2015	(r289610)
@@ -72,6 +72,18 @@ enum ntb_device_type {
 	NTB_SOC
 };
 
+/* ntb_conn_type are hardware numbers, cannot change. */
+enum ntb_conn_type {
+	NTB_CONN_TRANSPARENT = 0,
+	NTB_CONN_B2B = 1,
+	NTB_CONN_RP = 2,
+};
+
+enum ntb_b2b_direction {
+	NTB_DEV_USD = 0,
+	NTB_DEV_DSD = 1,
+};
+
 enum ntb_bar {
 	NTB_CONFIG_BAR = 0,
 	NTB_B2B_BAR_1,
@@ -173,9 +185,9 @@ struct ntb_softc {
 #define CTX_ASSERT(sc,f)	mtx_assert(&(sc)->ctx_lock, (f))
 	struct mtx		ctx_lock;
 
-	uint32_t ppd;
-	uint8_t conn_type;
-	uint8_t dev_type;
+	uint32_t		ppd;
+	enum ntb_conn_type	conn_type;
+	enum ntb_b2b_direction	dev_type;
 
 	/* Offset of peer bar0 in B2B BAR */
 	uint64_t			b2b_off;

Modified: head/sys/dev/ntb/ntb_hw/ntb_regs.h
==============================================================================
--- head/sys/dev/ntb/ntb_hw/ntb_regs.h	Tue Oct 20 01:45:57 2015	(r289609)
+++ head/sys/dev/ntb/ntb_hw/ntb_regs.h	Tue Oct 20 01:46:05 2015	(r289610)
@@ -149,13 +149,6 @@
 #define SOC_PPD_CONN_TYPE	0x0300
 #define SOC_PPD_DEV_TYPE	0x1000
 
-#define NTB_CONN_TRANSPARENT 	0
-#define NTB_CONN_B2B 		1
-#define NTB_CONN_RP 		2
-
-#define NTB_DEV_DSD	1
-#define NTB_DEV_USD	0
-
 /* All addresses are in low 32-bit space so 32-bit BARs can function */
 #define XEON_B2B_BAR0_USD_ADDR		0x1000000000000000ull
 #define XEON_B2B_BAR2_USD_ADDR64	0x2000000000000000ull



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