Date: Thu, 12 Sep 1996 11:38:32 -0700 (MST) From: Terry Lambert <terry@lambert.org> To: smp@csn.net (Steve Passe) Cc: terry@lambert.org, peter@spinner.dialix.com, rv@groa.uct.ac.za, freebsd-smp@FreeBSD.org Subject: Re: Intel XXpress - some SMP benchmarks Message-ID: <199609121838.LAA07343@phaeton.artisoft.com> In-Reply-To: <199609121823.MAA18695@clem.systemsix.com> from "Steve Passe" at Sep 12, 96 12:23:59 pm
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> >> One thing I'm not clear about from the IO apic docs yet is whether there > >> are 15 cpu's and 15 IO apic's, or whether there's a limit of 15 devices on > >> the APIC bus. > > > > 1 BP, 31 (AP | IO APIC) (2^5 == 32) > > its a four bit register, where do you get 2^5, am I missing something? Oh, ugh. Sequent supports 32 processors. I wonder how? Corrected value: 1 BP, 15 (AP | IO APIC) (2^4 == 16) > > You may want to disassemble your MP cold boot BIOS code to see about > > I've been wondering about the issue of the MP table being in BIOS. > Traditionally this is ROM. Do you think they just hardcode all this > stuff, or really arbitrate numbers during boot and can 'modify' them in the > BIOS area because it is really shadowed into RAM? Some of the stuff has to be arbitrary... the cache writeback/writethrough is enough to make me believe that. It changes with CMOS settings. Terry Lambert terry@lambert.org --- Any opinions in this posting are my own and not those of my present or previous employers.
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