Date: Wed, 28 Nov 2018 06:55:36 +0000 (UTC) From: Andrew Rybchenko <arybchik@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r341115 - head/sys/dev/sfxge/common Message-ID: <201811280655.wAS6taJY084413@repo.freebsd.org>
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Author: arybchik Date: Wed Nov 28 06:55:36 2018 New Revision: 341115 URL: https://svnweb.freebsd.org/changeset/base/341115 Log: sfxge(4): move Tx config to ef10 NIC board config Submitted by: Andy Moreton <amoreton at solarflare.com> Sponsored by: Solarflare Communications, Inc. Differential Revision: https://reviews.freebsd.org/D18191 Modified: head/sys/dev/sfxge/common/ef10_nic.c head/sys/dev/sfxge/common/hunt_nic.c head/sys/dev/sfxge/common/medford2_nic.c (contents, props changed) head/sys/dev/sfxge/common/medford_nic.c Modified: head/sys/dev/sfxge/common/ef10_nic.c ============================================================================== --- head/sys/dev/sfxge/common/ef10_nic.c Wed Nov 28 06:55:24 2018 (r341114) +++ head/sys/dev/sfxge/common/ef10_nic.c Wed Nov 28 06:55:36 2018 (r341115) @@ -1672,6 +1672,16 @@ ef10_nic_board_cfg( */ encp->enc_rx_scale_max_exclusive_contexts = 64 - 6; + encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT); + /* No boundary crossing limits */ + encp->enc_tx_dma_desc_boundary = 0; + + /* + * Maximum number of bytes into the frame the TCP header can start for + * firmware assisted TSO to work. + */ + encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT; + /* Get remaining controller-specific board config */ if ((rc = enop->eno_board_cfg(enp)) != 0) Modified: head/sys/dev/sfxge/common/hunt_nic.c ============================================================================== --- head/sys/dev/sfxge/common/hunt_nic.c Wed Nov 28 06:55:24 2018 (r341114) +++ head/sys/dev/sfxge/common/hunt_nic.c Wed Nov 28 06:55:36 2018 (r341115) @@ -232,10 +232,6 @@ hunt_board_cfg( encp->enc_rx_buf_align_start = 1; encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */ - encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT); - /* No boundary crossing limits */ - encp->enc_tx_dma_desc_boundary = 0; - /* * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available @@ -280,12 +276,6 @@ hunt_board_cfg( } encp->enc_intr_vec_base = base; encp->enc_intr_limit = nvec; - - /* - * Maximum number of bytes into the frame the TCP header can start for - * firmware assisted TSO to work. - */ - encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT; if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0) goto fail7; Modified: head/sys/dev/sfxge/common/medford2_nic.c ============================================================================== --- head/sys/dev/sfxge/common/medford2_nic.c Wed Nov 28 06:55:24 2018 (r341114) +++ head/sys/dev/sfxge/common/medford2_nic.c Wed Nov 28 06:55:36 2018 (r341115) @@ -166,10 +166,6 @@ medford2_board_cfg( } encp->enc_rx_buf_align_end = end_padding; - encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT); - /* No boundary crossing limits */ - encp->enc_tx_dma_desc_boundary = 0; - /* * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available @@ -215,12 +211,6 @@ medford2_board_cfg( } encp->enc_intr_vec_base = base; encp->enc_intr_limit = nvec; - - /* - * Maximum number of bytes into the frame the TCP header can start for - * firmware assisted TSO to work. - */ - encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT; /* * Medford2 stores a single global copy of VPD, not per-PF as on Modified: head/sys/dev/sfxge/common/medford_nic.c ============================================================================== --- head/sys/dev/sfxge/common/medford_nic.c Wed Nov 28 06:55:24 2018 (r341114) +++ head/sys/dev/sfxge/common/medford_nic.c Wed Nov 28 06:55:36 2018 (r341115) @@ -163,10 +163,6 @@ medford_board_cfg( } encp->enc_rx_buf_align_end = end_padding; - encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT); - /* No boundary crossing limits */ - encp->enc_tx_dma_desc_boundary = 0; - /* * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available @@ -212,12 +208,6 @@ medford_board_cfg( } encp->enc_intr_vec_base = base; encp->enc_intr_limit = nvec; - - /* - * Maximum number of bytes into the frame the TCP header can start for - * firmware assisted TSO to work. - */ - encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT; /* * Medford stores a single global copy of VPD, not per-PF as on
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