Date: Wed, 1 Nov 2017 02:54:49 +0000 (UTC) From: Justin Hibbits <jhibbits@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r325259 - in head/sys/powerpc: include powerpc Message-ID: <201711010254.vA12snJO059313@repo.freebsd.org>
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Author: jhibbits Date: Wed Nov 1 02:54:48 2017 New Revision: 325259 URL: https://svnweb.freebsd.org/changeset/base/325259 Log: Add Guest State (GS) bit to MSR bits For completeness only. It will be used by a hypervisor if/when one is written. While here, sort the MSR bits into the proper categories. Modified: head/sys/powerpc/include/psl.h head/sys/powerpc/powerpc/genassym.c Modified: head/sys/powerpc/include/psl.h ============================================================================== --- head/sys/powerpc/include/psl.h Wed Nov 1 02:40:15 2017 (r325258) +++ head/sys/powerpc/include/psl.h Wed Nov 1 02:54:48 2017 (r325259) @@ -45,15 +45,16 @@ #define PSL_FP 0x00002000UL /* floating point enable */ #define PSL_ME 0x00001000UL /* machine check enable */ #define PSL_FE0 0x00000800UL /* floating point interrupt mode 0 */ -#define PSL_BE 0x00000200UL /* branch trace enable */ #define PSL_FE1 0x00000100UL /* floating point interrupt mode 1 */ #define PSL_PMM 0x00000004UL /* performance monitor mark */ +#define PSL_RI 0x00000002UL /* recoverable interrupt */ /* Machine State Register - Book-E cores */ #ifdef __powerpc64__ #define PSL_CM 0x80000000UL /* Computation Mode (64-bit) */ #endif +#define PSL_GS 0x10000000UL /* Guest state */ #define PSL_UCLE 0x04000000UL /* User mode cache lock enable */ #define PSL_WE 0x00040000UL /* Wait state enable */ #define PSL_CE 0x00020000UL /* Critical interrupt enable */ @@ -72,10 +73,10 @@ #define PSL_POW 0x00040000UL /* power management */ #define PSL_ILE 0x00010000UL /* interrupt endian mode (1 == le) */ #define PSL_SE 0x00000400UL /* single-step trace enable */ +#define PSL_BE 0x00000200UL /* branch trace enable */ #define PSL_IP 0x00000040UL /* interrupt prefix - 601 only */ #define PSL_IR 0x00000020UL /* instruction address relocation */ #define PSL_DR 0x00000010UL /* data address relocation */ -#define PSL_RI 0x00000002UL /* recoverable interrupt */ #define PSL_LE 0x00000001UL /* endian mode (1 == le) */ /* Modified: head/sys/powerpc/powerpc/genassym.c ============================================================================== --- head/sys/powerpc/powerpc/genassym.c Wed Nov 1 02:40:15 2017 (r325258) +++ head/sys/powerpc/powerpc/genassym.c Wed Nov 1 02:54:48 2017 (r325259) @@ -225,6 +225,7 @@ ASSYM(MAXCOMLEN, MAXCOMLEN); #ifdef __powerpc64__ ASSYM(PSL_CM, PSL_CM); #endif +ASSYM(PSL_GS, PSL_GS); ASSYM(PSL_DE, PSL_DE); ASSYM(PSL_DS, PSL_DS); ASSYM(PSL_IS, PSL_IS);
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