Date: Sun, 15 Aug 2004 11:03:35 +0200 From: des@des.no (=?iso-8859-1?q?Dag-Erling_Sm=F8rgrav?=) To: Doug White <dwhite@gumbysoft.com> Cc: Andrew Gallatin <gallatin@cs.duke.edu> Subject: Re: Is the TSC timecounter safe on SMP system? Message-ID: <xzpbrhchixk.fsf@dwp.des.no> In-Reply-To: <20040813103710.F93695@carver.gumbysoft.com> (Doug White's message of "Fri, 13 Aug 2004 10:38:29 -0700 (PDT)") References: <16668.61707.474283.639200@grasshopper.cs.duke.edu> <20040813103710.F93695@carver.gumbysoft.com>
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Doug White <dwhite@gumbysoft.com> writes: > On Fri, 13 Aug 2004, Andrew Gallatin wrote: > > I have a system where the TSC timecounter is quite a bit more accurate > > (or perhaps its just much cheaper) than the ACPI timecounter. This is a > > single CPU, HTT system running an SMP kernel. > > [...] > > 1) Is it safe to switch to TSC? > If you like your ticks bouncing around; you'll get different values > depending on which CPU you read. Not necessarily; some SMP motherboards keep the TSCs synchronized. On those systems, you can set the kern.timecounter.smp_tsc tunable to a non-zero value to make the TSC eligible. It defaults to 1 on single- CPU systems, but the TSC code can't tell the difference between an HTT-enabled single-CPU box and a dual-CPU box, so you have to force it on HTT-enabled systems. DES --=20 Dag-Erling Sm=F8rgrav - des@des.no
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