Date: Wed, 10 Aug 2011 16:20:17 GMT From: Jakub Wojciech Klama <jceel@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 197475 for review Message-ID: <201108101620.p7AGKH8Y065804@skunkworks.freebsd.org>
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http://p4web.freebsd.org/@@197475?ac=10 Change 197475 by jceel@jceel_cyclone on 2011/08/10 16:19:17 Fixes in if_lpe: * MAC address is now read from FDT tree * Refactored some hardcoded values to #defines Affected files ... .. //depot/projects/soc2011/jceel_lpc/sys/arm/lpc/if_lpe.c#5 edit .. //depot/projects/soc2011/jceel_lpc/sys/arm/lpc/if_lpereg.h#4 edit .. //depot/projects/soc2011/jceel_lpc/sys/arm/lpc/lpcreg.h#10 edit .. //depot/projects/soc2011/jceel_lpc/sys/boot/fdt/dts/ea3250.dts#11 edit Differences ... ==== //depot/projects/soc2011/jceel_lpc/sys/arm/lpc/if_lpe.c#5 (text+ko) ==== @@ -114,6 +114,7 @@ struct lpe_softc { struct ifnet * lpe_ifp; struct mtx lpe_mtx; + phandle_t lpe_ofw; device_t lpe_dev; device_t lpe_miibus; uint8_t lpe_enaddr[6]; @@ -158,7 +159,6 @@ static int lpe_ifmedia_upd(struct ifnet *); static void lpe_ifmedia_sts(struct ifnet *, struct ifmediareq *); - #define lpe_lock(_sc) mtx_lock(&(_sc)->lpe_mtx) #define lpe_unlock(_sc) mtx_unlock(&(_sc)->lpe_mtx) #define lpe_lock_assert(sc) mtx_assert(&(_sc)->lpe_mtx, MA_OWNED) @@ -184,17 +184,21 @@ { struct lpe_softc *sc = device_get_softc(dev); struct ifnet *ifp; - int rid; + int rid, i; uint32_t val; sc->lpe_dev = dev; + sc->lpe_ofw = ofw_bus_get_node(dev); - sc->lpe_enaddr[0] = 0x00; - sc->lpe_enaddr[1] = 0x1a; - sc->lpe_enaddr[2] = 0xf1; - sc->lpe_enaddr[3] = 0x01; - sc->lpe_enaddr[4] = 0x1f; - sc->lpe_enaddr[5] = 0x23; + i = OF_getprop(sc->lpe_ofw, "local-mac-address", (void *)&sc->lpe_enaddr, 6); + if (i != 6) { + sc->lpe_enaddr[0] = 0x00; + sc->lpe_enaddr[1] = 0x11; + sc->lpe_enaddr[2] = 0x22; + sc->lpe_enaddr[3] = 0x33; + sc->lpe_enaddr[4] = 0x44; + sc->lpe_enaddr[5] = 0x55; + } mtx_init(&sc->lpe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF); @@ -250,7 +254,11 @@ } /* Enable Ethernet clock */ - lpc_pwr_write(dev, LPC_CLKPWR_MACCLK_CTRL, 0x1f); /* XXX */ + lpc_pwr_write(dev, LPC_CLKPWR_MACCLK_CTRL, + LPC_CLKPWR_MACCLK_CTRL_REG | + LPC_CLKPWR_MACCLK_CTRL_SLAVE | + LPC_CLKPWR_MACCLK_CTRL_MASTER | + LPC_CLKPWR_MACCLK_CTRL_HDWINF(3)); /* Reset chip */ lpe_reset(sc); @@ -550,7 +558,8 @@ if (i == nsegs - 1) { hwd->lhr_control |= LPE_HWDESC_LASTFLAG; hwd->lhr_control |= LPE_HWDESC_INTERRUPT; - hwd->lhr_control |= (1 << 28) | (1 << 29); // XXX + hwd->lhr_control |= LPE_HWDESC_CRC; + hwd->lhr_control |= LPE_HWDESC_PAD; } LPE_INC(prod, LPE_TXDESC_NUM); ==== //depot/projects/soc2011/jceel_lpc/sys/arm/lpc/if_lpereg.h#4 (text+ko) ==== @@ -158,6 +158,8 @@ /* These are valid for Tx descriptors only */ #define LPE_HWDESC_INTERRUPT (1 << 31) +#define LPE_HWDESC_CRC (1 << 29) +#define LPE_HWDESC_PAD (1 << 28) /* These are valid for Rx descriptors only */ #define LPE_HWDESC_CONTROL (1 << 18) ==== //depot/projects/soc2011/jceel_lpc/sys/arm/lpc/lpcreg.h#10 (text+ko) ==== @@ -28,6 +28,8 @@ #define _ARM_LPC_LPCREG_H #define LPC_DEV_PHYS_BASE 0x40000000 +#define LPC_DEV_P5_PHYS_BASE 0x20000000 +#define LPC_DEV_P6_PHYS_BASE 0x30000000 #define LPC_DEV_BASE 0xd0000000 #define LPC_DEV_SIZE 0x10000000 @@ -144,6 +146,10 @@ #define LPC_CLKPWR_DMACLK_CTRL_EN (1 << 0) #define LPC_CLKPWR_FLASHCLK_CTRL 0xc8 #define LPC_CLKPWR_MACCLK_CTRL 0x90 +#define LPC_CLKPWR_MACCLK_CTRL_REG (1 << 0) +#define LPC_CLKPWR_MACCLK_CTRL_SLAVE (1 << 1) +#define LPC_CLKPWR_MACCLK_CTRL_MASTER (1 << 2) +#define LPC_CLKPWR_MACCLK_CTRL_HDWINF(_n) ((_n & 0x3) << 3) #define LPC_CLKPWR_LCDCLK_CTRL 0x54 #define LPC_CLKPWR_LCDCLK_CTRL_DISPTYPE (1 << 8) #define LPC_CLKPWR_LCDCLK_CTRL_MODE(_n) ((_n & 0x3) << 6) @@ -205,6 +211,7 @@ /* * MMC/SD controller. (from UM10326: LPC32x0 User manual, page 436) */ +#define LPC_SD_BASE (LPC_DEV_P5_PHYS_BASE + 0x98000) #define LPC_SD_CLK (13 * 1000 * 1000) // 13Mhz #define LPC_SD_POWER 0x00 #define LPC_SD_POWER_OPENDRAIN (1 << 6) @@ -560,6 +567,9 @@ #define LPC_DMAC_SOFTLBREQ 0x28 #define LPC_DMAC_SOFTLSREQ 0x2c #define LPC_DMAC_CONFIG 0x30 +#define LPC_DMAC_CONFIG_M1 (1 << 2) +#define LPC_DMAC_CONFIG_M0 (1 << 1) +#define LPC_DMAC_CONFIG_ENABLE (1 << 0) #define LPC_DMAC_CHADDR(_n) (0x100 + (_n * 0x20)) #define LPC_DMAC_CHNUM 8 #define LPC_DMAC_CHSIZE 0x20 @@ -593,4 +603,25 @@ #define LPC_DMAC_CH_CONFIG_SRCP(_n) ((_n & 0x1f) << 1) #define LPC_DMAC_CH_CONFIG_E (1 << 0) +/* DMA peripheral ID's */ +#define LPC_DMAC_I2S0_DMA0_ID 0 +#define LPC_DMAC_NAND_ID 1 +#define LPC_DMAC_IS21_DMA0_ID 2 +#define LPC_DMAC_SSP1_ID 3 +#define LPC_DMAC_SPI2_ID 3 +#define LPC_DMAC_SD_ID 4 +#define LPC_DMAC_UART1_TX_ID 5 +#define LPC_DMAC_UART1_RX_ID 6 +#define LPC_DMAC_UART2_TX_ID 7 +#define LPC_DMAC_UART2_RX_ID 8 +#define LPC_DMAC_UART7_TX_ID 9 +#define LPC_DMAC_UART7_RX_ID 10 +#define LPC_DMAC_I2S1_DMA1_ID 10 +#define LPC_DMAC_SPI1_ID 11 +#define LPC_DMAC_SSP1_TX_ID 11 +#define LPC_DMAC_NAND2_ID 12 +#define LPC_DMAC_I2S0_DMA1_ID 13 +#define LPC_DMAC_SSP0_RX 14 +#define LPC_DMAC_SSP0_TX 15 + #endif /* _ARM_LPC_LPCREG_H */ ==== //depot/projects/soc2011/jceel_lpc/sys/boot/fdt/dts/ea3250.dts#11 (text+ko) ==== @@ -179,9 +179,9 @@ compatible = "simple-bus"; ranges = <0x0 0x30000000 0x10000000>; - dmac@100000 { + dmac@1000000 { compatible = "lpc,dmac"; - reg = <0x100000 0x20000>; + reg = <0x1000000 0x20000>; interrupts = <28>; interrupt-parent = <&PIC>; }; @@ -218,6 +218,7 @@ reg = <0x1060000 0x20000>; interrupts = <29>; interrupt-parent = <&PIC>; + local-mac-address = [ 00 1a f1 01 1f 23 ]; mdio@0 { #address-cells = <1>;
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