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Date:      Tue, 24 Oct 2017 06:49:07 +0000 (UTC)
From:      Dimitry Andric <dim@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-11@freebsd.org
Subject:   svn commit: r324946 - stable/11/contrib/llvm/lib/Target/AArch64
Message-ID:  <201710240649.v9O6n72b099327@repo.freebsd.org>
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Author: dim
Date: Tue Oct 24 06:49:06 2017
New Revision: 324946
URL: https://svnweb.freebsd.org/changeset/base/324946

Log:
  MFC r324826:
  
  Pull in r316035 from upstream llvm trunk (by Tim Northover):
  
    AArch64: account for possible frame index operand in compares.
  
    If the address of a local is used in a comparison, AArch64 can fold
    the address-calculation into the comparison via "adds".
    Unfortunately, a couple of places (both hit in this one test) are not
    ready to deal with that yet and just assume the first source operand
    is a register.
  
  This should fix an assertion failure while building the test suite of
  www/firefox for AArch64.
  
  PR:		223048

Modified:
  stable/11/contrib/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
  stable/11/contrib/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
Directory Properties:
  stable/11/   (props changed)

Modified: stable/11/contrib/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
==============================================================================
--- stable/11/contrib/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp	Tue Oct 24 05:41:48 2017	(r324945)
+++ stable/11/contrib/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp	Tue Oct 24 06:49:06 2017	(r324946)
@@ -940,6 +940,12 @@ bool AArch64InstrInfo::areMemAccessesTriviallyDisjoint
 bool AArch64InstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
                                       unsigned &SrcReg2, int &CmpMask,
                                       int &CmpValue) const {
+  // The first operand can be a frame index where we'd normally expect a
+  // register.
+  assert(MI.getNumOperands() >= 2 && "All AArch64 cmps should have 2 operands");
+  if (!MI.getOperand(1).isReg())
+    return false;
+
   switch (MI.getOpcode()) {
   default:
     break;

Modified: stable/11/contrib/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
==============================================================================
--- stable/11/contrib/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp	Tue Oct 24 05:41:48 2017	(r324945)
+++ stable/11/contrib/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp	Tue Oct 24 06:49:06 2017	(r324946)
@@ -167,6 +167,9 @@ AArch64RedundantCopyElimination::knownRegValInBlock(
     // CMP is an alias for SUBS with a dead destination register.
     case AArch64::SUBSWri:
     case AArch64::SUBSXri: {
+      // Sometimes the first operand is a FrameIndex. Bail if tht happens.
+      if (!PredI.getOperand(1).isReg())
+        return None;
       MCPhysReg SrcReg = PredI.getOperand(1).getReg();
 
       // Must not be a symbolic immediate.

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